High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on interfacial reliability of TSV structures. First, three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results From finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties are discussed.Aerospace Engineerin

Characterization Of Thermal Stresses And Plasticity In Through-Silicon Via Structures For Three-Dimensional Integration

Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in the TSV structure to cause reliability problems. In this study, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure. The thermo-mechanical characteristics of the Cu TSV structure were correlated to microstructure evolution during thermal cycling and the local plasticity in Cu in a triaxial stress state. These findings were confirmed by microstructure analysis of the Cu vias and finite element analysis (FEA) of the stress characteristics. In addition, the local plasticity and deformation in and around individual TSVs were measured by synchrotron x-ray microdiffraction to supplement the wafer curvature measurements. The importance and implication of the local plasticity and residual stress on TSV reliabilities are discussed for TSV extrusion and device keep-out zone (KOZ).Microelectronics Research Cente

Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted

Thermomechanical Characterization And Modeling For TSV Structures

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.Microelectronics Research Cente

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Design of TSV-sharing topologies for cost-effective 3D networks-on-chip

The Through-Silicon Via (TSV) technology has led to major breakthroughs in 3D stacking by providing higher speed and bandwidth, as well as lower power dissipation for the inter-layer communication. However, the current TSV fabrication suffers from a considerable area footprint and yield loss. Thus, it is necessary to restrict the number of TSVs in order to design cost-effective 3D on-chip networks. This critical issue can be addressed by clustering the network such that all of the routers within each cluster share a single TSV pillar for the vertical packet transmission. In some of the existing topologies, additional cluster routers are augmented into the mesh structure to handle the shared TSVs. However, they impose either performance degradation or power/area overhead to the system. Furthermore, the resulting architecture is no longer a mesh. In this paper, we redefine the clusters by replacing some routers in the mesh with the cluster routers, such that the mesh structure is preserved. The simulation results demonstrate a better equilibrium between performance and cost, using the proposed models

Technologies for 3D Heterogeneous Integration

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838