High On/Off Ratio Graphene Nanoconstriction Field Effect Transistor

We report a method to pattern monolayer graphene nanoconstriction field effect transistors (NCFETs) with critical dimensions below 10 nm. NCFET fabrication is enabled by the use of feedback controlled electromigration (FCE) to form a constriction in a gold etch mask that is first patterned using conventional lithographic techniques. The use of FCE allows the etch mask to be patterned on size scales below the limit of conventional nanolithography. We observe the opening of a confinement-induced energy gap as the NCFET width is reduced, as evidenced by a sharp increase in the NCFET on/off ratio. The on/off ratios we obtain with this procedure can be larger than 1000 at room temperature for the narrowest devices; this is the first report of such large room temperature on/off ratios for patterned graphene FETs.Comment: 18 pages, 6 figures, to appear in Smal

Application of Graphene within Optoelectronic Devices and Transistors

Scientists are always yearning for new and exciting ways to unlock graphene's true potential. However, recent reports suggest this two-dimensional material may harbor some unique properties, making it a viable candidate for use in optoelectronic and semiconducting devices. Whereas on one hand, graphene is highly transparent due to its atomic thickness, the material does exhibit a strong interaction with photons. This has clear advantages over existing materials used in photonic devices such as Indium-based compounds. Moreover, the material can be used to 'trap' light and alter the incident wavelength, forming the basis of the plasmonic devices. We also highlight upon graphene's nonlinear optical response to an applied electric field, and the phenomenon of saturable absorption. Within the context of logical devices, graphene has no discernible band-gap. Therefore, generating one will be of utmost importance. Amongst many others, some existing methods to open this band-gap include chemical doping, deformation of the honeycomb structure, or the use of carbon nanotubes (CNTs). We shall also discuss various designs of transistors, including those which incorporate CNTs, and others which exploit the idea of quantum tunneling. A key advantage of the CNT transistor is that ballistic transport occurs throughout the CNT channel, with short channel effects being minimized. We shall also discuss recent developments of the graphene tunneling transistor, with emphasis being placed upon its operational mechanism. Finally, we provide perspective for incorporating graphene within high frequency devices, which do not require a pre-defined band-gap.Comment: Due to be published in "Current Topics in Applied Spectroscopy and the Science of Nanomaterials" - Springer (Fall 2014). (17 pages, 19 figures

Introduction to Graphene Electronics -- A New Era of Digital Transistors and Devices

The speed of silicon-based transistors has reached an impasse in the recent decade, primarily due to scaling techniques and the short-channel effect. Conversely, graphene (a revolutionary new material possessing an atomic thickness) has been shown to exhibit a promising value for electrical conductivity. Graphene would thus appear to alleviate some of the drawbacks associated with silicon-based transistors. It is for this reason why such a material is considered one of the most prominent candidates to replace silicon within nano-scale transistors. The major crux here, is that graphene is intrinsically gapless, and yet, transistors require a band-gap pertaining to a well-defined ON/OFF logical state. Therefore, exactly as to how one would create this band-gap in graphene allotropes is an intensive area of growing research. Existing methods include nano-ribbons, bilayer and multi-layer structures, carbon nanotubes, as well as the usage of the graphene substrates. Graphene transistors can generally be classified according to two working principles. The first is that a single graphene layer, nanoribbon or carbon nanotube can act as a transistor channel, with current being transported along the horizontal axis. The second mechanism is regarded as tunneling, whether this be band-to-band on a single graphene layer, or vertically between adjacent graphene layers. The high-frequency graphene amplifier is another talking point in recent research, since it does not require a clear ON/OFF state, as with logical electronics. This paper reviews both the physical properties and manufacturing methodologies of graphene, as well as graphene-based electronic devices, transistors, and high-frequency amplifiers from past to present studies. Finally, we provide possible perspectives with regards to future developments.Comment: This is an updated version of our review article, due to be published in Contemporary Physics (Sept 2013). Included are updated references, along with a few minor corrections. (45 pages, 19 figures

Self-aligned 0.12mm T-gate In.53Ga.47As/In.52Al.48As HEMT Technology Utilising a Non Annealed Ohmic Contact Strategy

An InGaAs/InAlAs based HEMT structure, lattice matched to an InP substrate, is presented in which drive current and transconductance has been optimized through a double-delta doping strategy. Together with an increase in channel carrier density, this allows the use of a non-annealed ohmic contact process. HEMT devices with 120 nm standard and self-aligned T-gates were fabricated using the non-annealed ohmic process. At DC, self-aligned and standard devices exhibited transconductances of up to 1480 and 1100 mS/mm respectively, while both demonstrated current densities in the range 800 mA/mm. At RF, a cutoff frequency f/sub T/ of 190 GHz was extracted for the self-aligned device. The DC characteristics of the standard devices were then calibrated and modelled using a compound semiconductor Monte Carlo device simulator. MC simulations provide insight into transport within the channel and illustrate benefits over a single delta doped structure

Analytical current Model for Dual Material Double Gate Junctionless Transistor

A Transistor model with bulk current is proposed in this article for long channel dual material double gate junction less transistor. The influence of different device parameters such as body thickness, channel length, oxide thickness, and the doping density on bulk current is investigated. The proposed model is validated and compared with simulated data using Cogenda TCAD. The model is designed by Poison’s equation and depletion approximation. Current driving capability of MOSFET is improved by dual material gate compare to single material gate