Design implementation and measurement of a collision avoidance multiple broadcast tree network

Packet collisions and their resolution create a performance bottleneck in random access LANs. Collision avoidance switches are a hardware solution to this problem [1, 2]. Collision avoidance switches allow the implementation of random access protocols without the penalty of collisions among packets.In this paper, we describe a design and implementation of a local area network architecture based on collision avoidance, called the Collision Avoidance Multiple Broadcast (CAMB) tree network. Our implementation follows the protocol layering architecture of the IEEE 802 local area networks, and includes CAMB tree switches, station/network interface boards, and support of transport protocols. We also present the performance measurements of our experimental CAMB tree network

A user oriented microcomputer facility for designing linear quadratic Gaussian feedback compensators

A laboratory design facility for digital microprocessor implementation of linear-quadratic-Gaussian feedback compensators is described. Outputs from user interactive programs for solving infinite time horizon LQ regulator and Kalman filter problems were conditioned for implementation on the laboratory microcomputer system. The software consisted of two parts: an offline high-level program for solving the LQ Ricatti equations and generating associated feedback and filter gains and a cross compiler/macro assembler which generates object code for the target microprocessor system. A PDP 11/70 with a UNIX operating system was used for all high level program and data management, and the target microprocessor system is an Intel MDS (8080-based processor). Application to the control of a two dimensional inverted pendulum is presented and issues in expanding the design/prototyping system to other target machine architectures are discussed

Adaptive Latency Insensitive Protocols

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

Avionics test bed development plan

A development plan for a proposed avionics test bed facility for the early investigation and evaluation of new concepts for the control of large space structures, orbiter attached flex body experiments, and orbiter enhancements is presented. A distributed data processing facility that utilizes the current laboratory resources for the test bed development is outlined. Future studies required for implementation, the management system for project control, and the baseline system configuration are defined. A background analysis of the specific hardware system for the preliminary baseline avionics test bed system is included

Simulation and control engineering studies of NASA-Ames 40 foot by 80 foot/80 foot by 120 foot wind tunnels

The development and use of a digital computer simulation of the proposed wind tunnel facility is described. The feasibility of automatic control of wind tunnel airspeed and other parameters was examined. Specifications and implementation recommendations for a computer based automatic control and monitoring system are presented

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller