Design of an Efficient Viterbi Decoder using Xilinx

The vision of wireless communication is to provide high-speed and high-quality exchange of information between two portable devices located anywhere in the world. In this hectic and unsecure world you need to be sure your data is not only safe and secure but that you are working with it at the highest possible speed. Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. The two decoding algorithms used for decoding the convolutional codes are Viterbi algorithm and Sequential algorithm. Sequential decoding has advantage that it can perform very well with long constraint length convolutional codes, but it has a variable decoding time. Viterbi decoding technique is used for decoding the convolutional codes but with the limitation to constraint length. It requires smaller constraint length. The Viterbi algorithm is the most extensively employed decoding algorithm for convolution codes. In digital communication and signal processing the estimation and detection of problems is done by using viterbi algorithm. The Viterbi decoding algorithm is widely used in radio communication, radio relay and satellite communication. This thesis represents the implementation of hard decision Viterbi decoding with constraint length 7 and code rate ½ and its algorithm. The decoder architecture is defined in VHDL and the circuit is simulated and synthesized on Xilinx 14.7

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance