Memory Module Design for High-Temperature Applications in SiC CMOS Technology

The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is required to realize a complete electronic system in SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. A novel static random-access memory (SRAM) cell is designed and implemented in a SiC 1 µm triple well CMOS process for high-temperature applications in this work. The prevalent issues encountered during SiC fabrication and the uncertainties in device performance led to 6T SRAM cell design modifications that enable adaptability to the worst and the best cases. However, design trade-offs are made in the design size, the number of transistors, number of I/Os, and the cell\u27s power consumption. The novel SRAM cell design mitigates the effect of poor p-type contacts after the device fabrication by controlling the cell\u27s drive strength via an additional pull-up network. The design also includes two parallel access transistors and separate wordlines that control both access transistors. This individual control enables post-fabrication tunability in the cell ratio (CR) and the pull-up (PR) ratio of the cell. It also allows tuning the access transistors\u27 effective width during a data read operation, and a data write operation, independently. Along with the SRAM cell design, the conventional latch-based sense amplifier is also designed in the SiC CMOS process to realize the monolithic memory IC modules. The SRAM cell performance is evaluated on the basis of static noise margin (SNM), write SNM (WSNM), read SNM (RSNM), leakage current, and read access time over a wide temperature range (25ºC to 500ºC) on three uniquely processed wafers. The noise margins measured on Wafer #2 show a lower leakage current of ~500 nA at 500ºC with the supply voltage of 10 V. The SNM of 6.07 V is measured at 500ºC with a 10 V of power supply. The read access time at 400ºC is ~7.5 µs at a supply voltage of 10 V

Multi-port Memory Design for Advanced Computer Architectures

In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters. Multi-porting is essential for caches and shared-data systems, especially multi-core System-on-chips (SOC). It can significantly increase the memory access throughput. We evaluate FinFET voltage-mode multi-port SRAM cells using different metrics including leakage current, static noise margin and read/write performance. Simulation results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over classical double-ended structures at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended multi-port structures can achieve equivalent write performance to the classical double-ended multi-port structure for 9% area overhead. Moreover, compared with CMOS SRAM, FinFET SRAM has better stability and standby power. We also describe new methods for the design of FinFET current-mode multi-port SRAM cells. Current-mode SRAMs avoid the full-swing of the bitline, reducing dynamic power and access time. However, that comes at the cost of voltage drop, which compromises stability. The design proposed in this thesis utilizes the feature of Independent Gate (IG) mode FinFET, which can leverage threshold voltage by controlling the back gate voltage, to merge two transistors into one through high-Vt and low-Vt transistors. This design not only reduces the voltage drop, but it also reduces the area in multi-port current-mode SRAM design. For off-chip memory, we propose a novel two-port 1-read, 1-write (1R1W) phasechange memory (PCM) cell, which significantly reduces the probability of blocking at the bank levels. Different from the traditional PCM cell, the access transistors are at the top and connected to the bitline. We use Verilog-A to model the behavior of Ge2Sb2Te5 (GST: the storage component). We evaluate the performance of the two-port cell by transistor sizing and voltage pumping. Simulation results show that pMOS transistor is more practical than nMOS transistor as the access device when both area and power are considered. The estimated area overhead is 1.7�, compared to single-port PCM cell. In brief, the contribution we make in this thesis is that we propose and evaluate three different kinds of multi-port memories that are favorable for advanced computer architectures

Robust low-power digital circuit design in nano-CMOS technologies

Device scaling has resulted in large scale integrated, high performance, low-power, and low cost systems. However the move towards sub-100 nm technology nodes has increased variability in device characteristics due to large process variations. Variability has severe implications on digital circuit design by causing timing uncertainties in combinational circuits, degrading yield and reliability of memory elements, and increasing power density due to slow scaling of supply voltage. Conventional design methods add large pessimistic safety margins to mitigate increased variability, however, they incur large power and performance loss as the combination of worst cases occurs very rarely. In-situ monitoring of timing failures provides an opportunity to dynamically tune safety margins in proportion to on-chip variability that can significantly minimize power and performance losses. We demonstrated by simulations two delay sensor designs to detect timing failures in advance that can be coupled with different compensation techniques such as voltage scaling, body biasing, or frequency scaling to avoid actual timing failures. Our simulation results using 45 nm and 32 nm technology BSIM4 models indicate significant reduction in total power consumption under temperature and statistical variations. Future work involves using dual sensing to avoid useless voltage scaling that incurs a speed loss. SRAM cache is the first victim of increased process variations that requires handcrafted design to meet area, power, and performance requirements. We have proposed novel 6 transistors (6T), 7 transistors (7T), and 8 transistors (8T)-SRAM cells that enable variability tolerant and low-power SRAM cache designs. Increased sense-amplifier offset voltage due to device mismatch arising from high variability increases delay and power consumption of SRAM design. We have proposed two novel design techniques to reduce offset voltage dependent delays providing a high speed low-power SRAM design. Increasing leakage currents in nano-CMOS technologies pose a major challenge to a low-power reliable design. We have investigated novel segmented supply voltage architecture to reduce leakage power of the SRAM caches since they occupy bulk of the total chip area and power. Future work involves developing leakage reduction methods for the combination logic designs including SRAM peripherals

A Novel variation-tolerant 9T SRAM design for nanoscale CMOS

As the feature sizes decrease, understanding manufacturing variations becomes essential to effectively design robust circuits. Manufacturing variations occur when process parameters deviate from their ideal or expected values, resulting in variations in device characteristics. Variations in the device characteristics cause the circuit to deviate from its expected behavior resulting in circuit instability, performance degradation, and yield loss. Both from an economic and performance standpoint, the yield and performance of Static Random Access Memories (SRAMs) are of great importance to the modern System-on-Chip designs. SRAM bitcells typically employ well-matched, minimum-sized transistors which make them highly sensitive to process variations. To overcome these challenges, researchers have proposed different topologies for SRAMs with 8T and 10T SRAM designs. These designs improve the cell stability but suffer from bitline-leakage noise, placing constraints on the number of cells shared by each bitline. These designs also have substantial area overhead when compared to the traditional 6T design. In this work, the published SRAM designs are characterized using commercial CMOS 65 nm models and are compared based on critical SRAM parameters like read stability, write stability, bitline leakage and the impact of process variations. Furthermore, a single-ended 9T SRAM design is proposed that enhances data stability and simultaneously addresses the bitline leakage problem. The proposed design also satisfies the yield criterion to achieve 90% yield for a 1Mb SRAM array in the presence of process variations