Real-Time FPGA-Based Testbed for Evaluating Digital Predistortion in Fully Digital MIMO Transmitters

As one of the key enabling technologies of 5G networks, massive multiple-input, multiple-output (MIMO) transmitters use many transmit chains to ensure a very high data rate and acceptable signal quality. Realizing Massive MIMO not only includes increasing antenna count but also requires proportionally more power amplifiers (PAs). Digital predistortion (DPD) is a well-established signal processing method that mitigates the non-linearities of a PA when operated near saturation. Design tradeoffs must be carefully considered to reduce the system's overall power requirements given the high PA count in MIMO systems. This implies DPD power consumption for each transmission chain must be minimized. Apart from this, larger transmission bandwidths in next-generation networks require high hardware clock rates on the order of a few gigahertz. Current hardware can satisfy clock rates of up to hundreds of megahertz. Thus, there is a need for parallelized signal processing methods to meet bandwidth requirements. This thesis investigates and addresses some challenges for deploying massive MIMO systems by designing and building a reconfigurable digital signal processing (DSP) testbed that allows for the implementation and validation of real-time DSP algorithms including DPD, for fully digital massive MIMO transceivers. This testbed allows transmission of up to 16 fully digital transmission chains at sub-6 GHz frequencies and supports up to 120 MHz of modulation bandwidths. Finally, a low-complexity and parallelized piecewise-linear (PWL) dual-input dual-output (DISO) DPD solution is proposed for linearizing MIMO transmitters. This DPD solution is realized with a commercially available field-programmable-gate-array (FPGA)

Contribution to dimensionality reduction of digital predistorter behavioral models for RF power amplifier linearization

The power efficiency and linearity of radio frequency (RF) power amplifiers (PAs) are critical in wireless communication systems. The main scope of PA designers is to build the RF PAs capable to maintain high efficiency and linearity figures simultaneously. However, these figures are inherently conflicted to each other and system-level solutions based on linearization techniques are required. Digital predistortion (DPD) linearization has become the most widely used solution to mitigate the efficiency versus linearity trade-off. The dimensionality of the DPD model depends on the complexity of the system. It increases significantly in high efficient amplification architectures when considering current wideband and spectrally efficient technologies. Overparametrization may lead to an ill-conditioned least squares (LS) estimation of the DPD coefficients, which is usually solved by employing regularization techniques. However, in order to both reduce the computational complexity and avoid ill-conditioning problems derived from overparametrization, several efforts have been dedicated to investigate dimensionality reduction techniques to reduce the order of the DPD model. This dissertation contributes to the dimensionality reduction of DPD linearizers for RF PAs with emphasis on the identification and adaptation subsystem. In particular, several dynamic model order reduction approaches based on feature extraction techniques are proposed. Thus, the minimum number of relevant DPD coefficients are dynamically selected and estimated in the DPD adaptation subsystem. The number of DPD coefficients is reduced, ensuring a well-conditioned LS estimation while demanding minimum hardware resources. The presented dynamic linearization approaches are evaluated and compared through experimental validation with an envelope tracking PA and a class-J PA The experimental results show similar linearization performance than the conventional LS solution but at lower computational cost.La eficiencia energetica y la linealidad de los amplificadores de potencia (PA) de radiofrecuencia (RF) son fundamentales en los sistemas de comunicacion inalambrica. El principal objetivo a alcanzar en el diserio de amplificadores de radiofrecuencia es lograr simultaneamente elevadas cifras de eficiencia y de linealidad. Sin embargo, estas cifras estan inherentemente en conflicto entre si, y se requieren soluciones a nivel de sistema basadas en tecnicas de linealizacion. La linealizacion mediante predistorsion digital (DPD) se ha convertido en la solucion mas utilizada para mitigar el compromise entre eficiencia y linealidad. La dimension del modelo del predistorsionador DPD depende de la complejidad del sistema, y aumenta significativamente en las arquitecturas de amplificacion de alta eficiencia cuando se consideran los actuales anchos de banda y las tecnologfas espectralmente eficientes. El exceso de parametrizacion puede conducir a una estimacion de los coeficientes DPD, mediante minimos cuadrados (LS), mal condicionada, lo cual generalmente se resuelve empleando tecnicas de regularizacion. Sin embargo, con el fin de reducir la complejidad computacional y evitar dichos problemas de mal acondicionamiento derivados de la sobreparametrizacion, se han dedicado varies esfuerzos para investigar tecnicas de reduccion de dimensionalidad que permitan reducir el orden del modelo del DPD. Esta tesis doctoral contribuye a aportar soluciones para la reduccion de la dimension de los linealizadores DPD para RF PA, centrandose en el subsistema de identificacion y adaptacion. En concrete, se proponen varies enfoques de reduccion de orden del modelo dinamico, basados en tecnicas de extraccion de caracteristicas. El numero minimo de coeficientes DPD relevantes se seleccionan y estiman dinamicamente en el subsistema de adaptacion del DPD, y de este modo la cantidad de coeficientes DPD se reduce, lo cual ademas garantiza una estimacion de LS bien condicionada al tiempo que exige menos recursos de hardware. Las propuestas de linealizacion dinamica presentados en esta tesis se evaluan y comparan mediante validacion experimental con un PA de seguimiento de envolvente y un PA tipo clase J. Los resultados experimentales muestran unos resultados de linealizacion de los PA similares a los obtenidos cuando se em plea la solucion LS convencional, pero con un coste computacional mas reducido.Postprint (published version

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Automatic transmit power control for power efficient communications in UAS

Nowadays, unmanned aerial vehicles (UAV) have become one of the most popular tools that can be used in commercial, scientific, agricultural and military applications. As drones become faster, smaller and cheaper, with the ability to add payloads, the usage of the drone can be versatile. In most of the cases, unmanned aerials systems (UAS) are equipped with a wireless communication system to establish a link with the ground control station to transfer the control commands, video stream, and payload data. However, with the limited onboard calculation resources in the UAS, and the growing size and volume of the payload data, computational complex signal processing such as deep learning cannot be easily done on the drone. Hence, in many drone applications, the UAS is just a tool for capturing and storing data, and then the data is post-processed off-line in a more powerful computing device. The other solution is to stream payload data to the ground control station (GCS) and let the powerful computer on the ground station to handle these data in real-time. With the development of communication techniques such as orthogonal frequency-division multiplexing (OFDM) and multiple-input multiple-output (MIMO) transmissions, it is possible to increase the spectral efficiency over large bandwidths and consequently achieve high transmission rates. However, the drone and the communication system are usually being designed separately, which means that regardless of the situation of the drone, the communication system is working independently to provide the data link. Consequently, by taking into account the position of the drone, the communication system has some room to optimize the link budget efficiency. In this master thesis, a power-efficient wireless communication downlink for UAS has been designed. It is achieved by developing an automatic transmit power control system and a custom OFDM communication system. The work has been divided into three parts: research of the drone communication system, an optimized communication system design and finally, FPGA implementation. In the first part, an overview on commercial drone communication schemes is presented and discussed. The advantages and disadvantages shown are the source of inspiration for improvement. With these ideas, an optimized scheme is presented. In the second part, an automatic transmit power control system for UAV wireless communication and a power-efficient OFDM downlink scheme are proposed. The automatic transmit power control system can estimate the required power level by the relative position between the drone and the GCS and then inform the system to adjust the power amplifier (PA) gain and power supply settings. To obtain high power efficiency for different output power levels, a searching strategy has been applied to the PA testbed to find out the best voltage supply and gain configurations. Besides, the OFDM signal generation developed in Python can encode data bytes to the baseband signal for testing purpose. Digital predistortion (DPD) linearization has been included in the transmitter’s design to guarantee the signal linearity. In the third part, two core algorithms: IFFT and LUT-based DPD, have been implemented in the FPGA platform to meet the real-time and high-speed I/O requirements. By using the high-level synthesis design process provided by Xilinx Corp, the algorithms are implemented as reusable IP blocks. The conclusion of the project is given in the end, including the summary of the proposed drone communication system and envisioning possible future lines of research

CCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communications

Satellite communications are a well-established research area in which the main innovation of last decade has been the use of multi-carrier modulations and more robust channel coding techniques. However, in recent years, novel advanced signal processing has started being developed for these communications due to the increase in the signal processing capacity of transmitters and receivers. Although signal processing capabilities are increasing, they are still constrained by large limitations because these techniques need to be implemented in real hardware, thus making complexity a matter of critical importance. Therefore, this paper presents the design and implementation of a transmitter with adaptable coding and modulation on a field-programmable-gate-array (FPGA). The main motivation came from the standard CCSDS 131.2-B-1 which recommends that such a novel transmitter which has to date not been implemented in a real system The system was modeled by MATLAB with the purpose of being programmed in VHDL following the AXI-stream protocol between components. Behavioral simulation results were obtained in VIVADO and compared with MATLAB for verification purposes. The transmitter logical circuit was synthesized in a FPGA Zynq Ultrascale RFSoC ZU28DR, showing low resource consumption and correct functioning, leading us to conclude that the deployment of new communication systems in state-of-the-art hardware in satellite communications is justified.The research was funded by Projects IRENE (PID2020-115323RB-C33) (MINECO/AEI/FEDER, UE) and MFOC (Madrid Flight on Chip "Innovation Cooperative Projects Comunidad of Madrid" HUBS 2018/ Madrid Flight on Chip)

DESIGN SPACE EXPLORATION FOR SIGNAL PROCESSING SYSTEMS USING LIGHTWEIGHT DATAFLOW GRAPHS

Digital signal processing (DSP) is widely used in many types of devices, including mobile phones, tablets, personal computers, and numerous forms of embedded systems. Implementation of modern DSP applications is very challenging in part due to the complex design spaces that are involved. These design spaces involve many kinds of configurable parameters associated with the signal processing algorithms that are used, as well as different ways of mapping the algorithms onto the targeted platforms. In this thesis, we develop new algorithms, software tools and design methodologies to systematically explore the complex design spaces that are involved in design and implementation of signal processing systems. To improve the efficiency of design space exploration, we develop and apply compact system level models, which are carefully formulated to concisely capture key properties of signal processing algorithms, target platforms, and algorithm-platform interactions. Throughout the thesis, we develop design methodologies and tools for integrating new compact system level models and design space exploration methods with lightweight dataflow (LWDF) techniques for design and implementation of signal processing systems. LWDF is a previously-introduced approach for integrating new forms of design space exploration and system-level optimization into design processes for DSP systems. LWDF provides a compact set of retargetable application programming interfaces (APIs) that facilitates the integration of dataflow-based models and methods. Dataflow provides an important formal foundation for advanced DSP system design, and the flexible support for dataflow in LWDF facilitates experimentation with and application of novel design methods that are founded in dataflow concepts. Our developed methodologies apply LWDF programming to facilitate their application to different types of platforms and their efficient integration with platform-based tools for hardware/software implementation. Additionally, we introduce novel extensions to LWDF to improve its utility for digital hardware design and adaptive signal processing implementation. To address the aforementioned challenges of design space exploration and system optimization, we present a systematic multiobjective optimization framework for dataflow-based architectures. This framework builds on the methodology of multiobjective evolutionary algorithms and derives key system parameters subject to time-varying and multidimensional constraints on system performance. We demonstrate the framework by applying LWDF techniques to develop a dataflow-based architecture that can be dynamically reconfigured to realize strategic configurations in the underlying parameter space based on changing operational requirements. Secondly, we apply Markov decision processes (MDPs) for design space exploration in adaptive embedded signal processing systems. We propose a framework, known as the Hierarchical MDP framework for Compact System-level Modeling (HMCSM), which embraces MDPs to enable autonomous adaptation of embedded signal processing under multidimensional constraints and optimization objectives. The framework integrates automated, MDP-based generation of optimal reconfiguration policies, dataflow-based application modeling, and implementation of embedded control software that carries out the generated reconfiguration policies. Third, we present a new methodology for design and implementation of signal processing systems that are targeted to system-on-chip (SoC) platforms. The methodology is centered on the use of LWDF concepts and methods for applying principles of dataflow design at different layers of abstraction. The development processes integrated in our approach are software implementation, hardware implementation, hardware-software co-design, and optimized application mapping. The proposed methodology facilitates development and integration of signal processing hardware and software modules that involve heterogeneous programming languages and platforms. Through three case studies involving complex applications, we demonstrate the effectiveness of the proposed contributions for compact system level design and design space exploration: a digital predistortion (DPD) system, a reconfigurable channelizer for wireless communication, and a deep neural network (DNN) for vehicle classification

Linearization techniques to suppress optical nonlinearity

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

Nonlinear impairments and mitigation technologies for the next generation fiber-wireless mobile fronthaul networks

The proliferation of Internet-connected mobile devices and video-intensive services are driving the growth of mobile data traffic in an explosive way. The last mile of access networks, mobile fronthaul (MFH) networks, have become the data rate bottleneck of user experience. The objective of this research are two-fold. For analog MFH, nonlinear interferences among multiple bands of mobile signals in a multi-RAT multi-service radio-over-fiber (RoF)-based MFH system are investigated for the first time. The nonlinear impairments of both single-carrier and multi-carrier signals are investigated, and it is experimentally demonstrated that inter-channel interferences play a more important role in the performance degradation of analog MFH than the nonlinear distortions of each individual signal. A digital predistortion technique was also presented to linearize the analog MFH links. On the other hand, for digital MFH, we experimentally demonstrate a novel digitization interface based on delta-sigma modulation to replace the state-of-the-art common public radio interface (CPRI). Compared with CPRI, it provides improved spectral efficiency and enhanced fronthaul capacity, and can accommodate both 4G-LTE and 5G mobile services.Ph.D

Linearization techniques to suppress optical nonlinearity

This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations.EThOS - Electronic Theses Online ServiceGBUnited Kingdo