Dark current spectroscopy of transition metals in CMOS image sensors

We have investigated the effects of deliberate heavymetals contamination on dark current and image defects in CMOS Image Sensors (CIS). Analysis of dark current in these imager dice has revealed different behaviors among most important 3d metals present in the process line. We have implanted directly in 3 Mega array pixels the following metals: Cr, V, Cu, Ni, Fe, Ti, Mo, W, Al and Zn. Analyzing the dark current "spectrum" as obtained for fixed integration periods of time by means of standard image-Testing equipment, these impurities can be identified and detected with a sensitivity of ∼ 109 traps/cm3 or higher

Reliability Studies of TiN/Hf-Silicate Based Gate Stacks

Hafnium-silicate based oxides are among the leading candidates to be included into the first generation of high-Κ gate stacks in nano-scale CMOS technology because of their distinct advantages as far as thermal stability, leakage characteristics, threshold stability and low mobility degradation are concerned. Their reliability, which is limited by trapping at pre-existing and stress induced defects, remains to be a major concern. Energy levels of electrically active ionic defects within the thick high-Κ have been experimentally observed in the context of MOS band diagram for the first time in Hf-silicate gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative- U transition occurs depending on bias condition. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping. Mixed degradation, due to trapping of both electrons and holes in the trap levels within the bulk high-K, was observed under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (ΔFB) with respect to stress time. Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (ΔVT) with respect to stress levels. For the incident carrier energies above the calculated 0 vacancy formation threshold and thick high-Κ layer, both flatband voltage shift, due to electron trapping at the deep levels, and increase in leakage current during stress follow tn(n ≈ 0.4) power-law dependence under substrate hot electron injection. Negative-U transitions to deep levels are shown to be responsible for the strong correlation between slow transient trapping and trap assisted tunneling. As far as negative bias temperature instability, NBTI effects on pMOSFETs is concerned, ΔVT is due to the mixed degradation within the bulk high-Κ for low bias conditions. For moderately high bias, ΔVT shows an excellent match with that of SiO, based devices, which is explained by reaction-diffusion (R-D) model of NBTL. Under high bias condition at elevated temperatures, due to high Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation. Time-zero dielectric breakdown (TZBD) characteristics of TiN/HfO2 based gate stacks show that thickness and growth conditions significantly affect the BD field of IL. For the thin high-w layers, BD of IL triggers BD of the gate stack. Otherwise, BD of high-w layer initiates it. During time dependent dielectric breakdown, TDDB, four regimes of degradation are observed under CVS with high gate bias conditions: (i) charge trapping/defect generation, (ii) soft breakdown (SBD), (iii) progressive breakdown and (iv) hard breakdown (HBD). Activation energy of bond-breakage, found from Arrhenius plots of 63% failure value of TBD, shows that IL degradation triggers gate stacks BD, and the wear-out during TDDB

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Infrared Photodetectors based on InSb and InAs Nanostructures via Heterogeneous Integration-Rapid Melt Growth and Template Assisted Selective Epitaxy

Monolithic heterogeneous integration of III-V semiconductors with the contemporary Si Complementary Metal Oxide Semiconductor (CMOS) technology has instigated a wide range of possibilities and functionalities in the semiconductor industry, in the field of digitalcircuits, optical sensors, light emitters, and high-frequency communication devices. However, the integration of III-V semiconductorsis not trivial due to the differences in lattice parameters, polarity, and thermal expansion coefficient. This thesis explores two integrationtechniques to form III-V nanostructures with potential applications in the infrared detection field.The first technique implemented in this thesis work is the Rapid Melt Growth technique. InSb, which has a large lattice mismatch(19%) to Si, is used to demonstrate the RMG integration technique. A flash lamp with a millisecond annealing technique is utilized tomelt and recrystallize amorphous InSb material to form a single crystalline material. The development of the fabrication process andthe experimental results for obtaining a single crystalline InSb-on-insulator from a Si seed area through the RMG process are presented.Electron Back Scatter Diffraction (EBSD) technique was employed to understand the crystal quality, orientation, and defects in theRMG InSb nanostructures. The InSb nanostructures have a resistivity of 10 mΩ cm, similar to the VLS-grown InSb nanowires.Mobility ranging from 3490 - 877 cm2/ V sec was extracted through Hall and Van der Pauw measurements. Finally, we report the firstmonolithic integrated InSb nanostructure photodetector on Si through the RMG process. Detailed optical and electrical characterizationof the device, including the spectrally resolved photocurrent and the temperature-dependent dark current, is studied. The thesis presentsan InSb photodetector with a stable photodetector with a responsivity of 0.5 A/W at 16 nW illumination and millisecond time response.The second integration technique implemented in this thesis work is Template Assisted Selective Epitaxy. Here, the versatility ofTASE technique to integrate InAs nanowires on W metal seed is demonstrated. This technique enables the feasibility of integratingIII-V semiconductors to back -end of the line integration with Si CMOS technology. EBSD technique was utilized to study andobtain the statistics on the single crystalline InAs nanowires grown from different diameter templates. We also demonstrate thepossibility of achieving an nBn InAs detector using TASE on W approach. This technique is a promising step towards developinghigh operating temperature (HOT) monolithic integrated mid-infrared detectors. Thus, the results of this thesis provide theperspective into two viable CMOS-compatible III-V integration techniques that could be utilized for photodetector applications at areduced cost

Reliability study of Zr and Al incorporated hf based high-k dielectric deposited by advanced processing

Hafnium-based high-x dielectric materials have been successfully used in the industry as a key replacement for SiO2 based gate dielectrics in order to continue CMOS device scaling to the 22-nm technology node. Further scaling according to the device roadmap requires the development of oxides with higher x values in order to scale the equivalent oxide thickness (EOT) to 0.7 nm or below while achieving low defect densities. In addition, next generation devices need to meet challenges like improved channel mobility, reduced gate leakage current, good control on threshold voltage, lower interface state density, and good reliability. In order to overcome these challenges, improvements of the high-x film properties and deposition methods are highly desirable. In this dissertation, a detail study of Zr and Al incorporated HfO2 based high-κ dielectrics is conducted to investigate improvement in electrical characteristics and reliability. To meet scaling requirements of the gate dielectric to sub 0.7 nm, Zr is added to HfO2 to form Hf1-xZrxO2 with x=0, 0.31 and 0.8 where the dielectric film is deposited by using various intermediate processing conditions, like (i) DADA: intermediate thermal annealing in a cyclical deposition process; (ii) DSDS: similar cyclical process with exposure to SPA Ar plasma; and (iii) As-Dep: the dielectric deposited without any intermediate step. MOSCAPs are formed with TiN metal gate and the reliability of these devices is investigated by subjecting them to a constant voltage stress in the gate injection mode. Stress induced flat-band voltage shift (ΔVFB), stress induced leakage current (SILC) and stress induced interface state degradation are observed. DSDS samples demonstrate the superior characteristics whereas the worst degradation is observed for DADA samples. Time dependent dielectric breakdown (TDDB) shows that DSDS Hf1-xZrxO2 (x=0.8) has the superior characteristics with reduced oxygen vacancy, which is affiliated to electron affinity variation in HfO2 and ZrO2. The trap activation energy levels estimated from the temperature dependent current voltage characteristics also support the observed reliability characteristics for these devices. In another experiment, HfO2 is lightly doped with Al with a variation in Al concentration by depositing intermediate HfAlOx layers. This work has demonstrated a high quality HfO2 based gate stack by depositing atomic layer deposited (ALD) HfAlOx along with HfO2 in a layered structure. In order to get multifold enhancement of the gate stack quality, both Al percentage and the distribution of Al are observed by varying the HfAlOx layer thickness and it is found that \u3c 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in the average EOT along with up to 41 % reduction in the gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increases the interface state density (Dit). When devices are stressed in the gate injection mode at a constant voltage stress, dielectrics with Al/(Hf+Al)% \u3c 2% show resistance to stress induced flat-band voltage shift (ΔVFB), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics show a higher charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability for devices with \u3c 2% Al/(Al+Hf)%

Si-based Germanium Tin Photodetectors for Short-Wave and Mid-Wave Infrared Detections

The demand of light-weight and inexpensive imaging system working in the infrared range keeps increasing for the last decade, especially for civil applications. Although several group IV materials such as silicon and germanium are used to realize detectors in the visible and near infrared region, they are not the efficient approach for imaging system in the short-wave infrared detection range and beyond due to bandgap limit. On the other hand, this market is heavily relied upon mature technology from III-V and II-VI elements over years, which are costly to growth and incompatible with available Si complementary metal-oxide-semiconductor (CMOS) foundries. This limits the fabrication of large scale focal plan arrays detectors in this detection range. Therefore, a material system that meets the necessary requirements has long been in demand. The Ge1-xSnx material system has been introduced as a potential solution for low-cost high-performance photodetector for short-wave infrared towards mid-infrared detections due to its compatibility with Si CMOS process and wide detection range by incorporating more Sn in the alloy. Since then, immense growth efforts have been made to improve the material quality reaching device-quality using commercial chemical vapor deposition (CVD) reactors or molecular beam epitaxy (MBE) chambers. This dissertation will develop Si-based GeSn photodetectors technology to realize low-cost high-performance focal plane arrays detectors working in the SWIR towards MIR. It began with the development of fabrication process of single element GeSn photoconductor and photodiode, followed by systematic characterization and analysis of detectors’ figures of merits to provide a more optimized structure. A peak responsivity of 20 A/W (photoconductor) and 0.34 A/W (photodiode) at 2 µm were achieved. An external quantum efficiency of 20 % was reported for the first time. The highest value of specific detectivity D* is only 3-4 times less than commercially available Extended-InGaAs detector. Surface passivation technique was also pursued to reduce surface leakage current. Finally, infrared imaging capability was demonstrated using single pixel detector. The study involves a wide range of Sn composition from 10 to 22 %

On border traps in back-side-illuminated CMOS image sensor oxides

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing E′ donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes:Modeling, Design, and Characterization

In this thesis we propose the use of photodiodes fabricated in planar technologies to address the detection problem in these applications. A number of solutions exist, optimized for these wavelengths, based on Germanium (Ge) and other III-V materials. In this thesis we focused on Ge thanks to its versatility and ease to use in the clean room. The main advantage of this material is in fact a good compatibility with Silicon and standard CMOS processes. Note that the proposed technology is not based on Silicon/Germanium (SiGe), whereby Ge is used to strain Si to achieve higher bandwidth in Si, not higher sensitivity. In our pure Ge approach, Ge is grafted onto Si (Ge-on-Si), achieving high responsivity at wavelengths of 900nm and higher. The proposed devices can operate in avalanche mode (avalanche photodiodes - APDs), and in Geiger mode (Geiger mode APDs (GAPDs) or single-photon avalanche diodes (SPADs)). To combine the advantages of Ge with single-photon sensitivity and excellent timing resolution of Si-based SPADs, this thesis proposes a new generation of SPADs, achieved in collaboration with Prof. Nanver at TUDelft, aimed at near-infrared range. The fabrication process of the Ge-on-Si SPAD approach, which we are investigating together with the TUDelft group, consists of a standard CMOS process combined with post-processing steps to grow Ge on top of a Si/SiO2 layer. In our study we have investigated the potential for a new generation of massively parallel, Ge-on-Si sensors fabricated in fully CMOS compatible technology. The objective was to address the next challenges of super-parallel pixel arrays, while exploiting the advantages of Ge substrate. The key technology developed in the thesis is a selective chemical-vapor deposition (CVD) epitaxial growth. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and pure-B depositions (PureGaB). The resulting p+n diodes have exceptionally good I-V characteristics with ideality factor of ~1.1 and low saturation currents. They can be operated both in proportional and in Geiger mode, and exhibit relatively low dark counts. We also looked at techniques to improve red and infrared sensitivity in conventional deep-submicron CMOS processes, by careful selection of standard layers at high depths in the Si substrate. Using the proposed approach, 12 µm-diameter SPADs were fabricated in 0.18µm CMOS technology showing low dark count rates (363 cps) at room temperature and considerably lower rates at cryogenic temperatures (77 K), while the FWHM timing jitter is as low as 76 ps. That of cryogenic SPADs is a novel research direction and in this thesis it was advocated as a significant trend for the future of optical sensing, especially in mid-infrared wavelengths. Low temperature characterizations reported in this thesis exposed how the relevant properties of fabrication materials, such as strength, thermal conductivity, ductility, and electrical resistance are changing. One of the most important properties is superconductivity in materials cooled to extreme temperatures: this is an important trend that will be pursued in the future activities of our group