Research on performance enhancement for electromagnetic analysis and power analysis in cryptographic LSI

制度:新 ; 報告番号:甲3785号 ; 学位の種類:博士(工学) ; 授与年月日:2012/11/19 ; 早大学位記番号:新6161Waseda Universit

Efeitos da falha lógica e fuga (dissipação de energia de área) em sistemas criptográficos usando a técnica de clock gating para aprimorar o protocolo na web

The last century has seen an evolution in technology that has improved communication systems and, in general, made life easier for people. Our communication systems have become faster and more dependable as a result of the explosion of gadgets and services. But, these upgrades come at a price. The power consumption is one of the most worrying costs. In recent years, the solution involved installing larger, more powerful batteries—so long as doing so did not limit mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as a “parasitic” leakage in a condition where there should ideally be no conduction. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality, this study suggests two novel techniques. It uses an optimization method based on threshold voltage change to reduce glitch power. A glitch-free circuit netlist is created using an algorithm, while still maintaining the requisite delay performance. Using this approach results in a 6.14% overall reduction in energy consumption.El siglo pasado fue testigo de una evolución de la tecnología que mejoró los sistemas de comunicación y, en general, facilitó la vida de las personas. Nuestros sistemas de comunicación se han vuelto más rápidos y confiables como resultado de la explosión de dispositivos y servicios. Pero, estas actualizaciones tienen un precio. El consumo de energía es uno de los costes más preocupantes. En los últimos años, la solución ha pasado por instalar baterías más grandes y potentes, siempre que esto no limite la movilidad. Los problemas económicos y ambientales actuales nos obligan a considerar soluciones alternativas, como métodos para reducir el consumo de energía de los dispositivos digitales. Este estudio se centra en el uso de circuitos digitales, que prometen ofrecer una buena eficiencia energética y un rendimiento deseable con un ahorro de tensión muy bajo. Se supone que ciertos interruptores digitales son redundantes y no necesarios para que el circuito funcione correctamente, pero continúan consumiendo energía. Por lo tanto, uno de los principales problemas para el diseño de bajo consumo es reducir estos conmutadores redundantes. La conducción por debajo del umbral en los circuitos digitales normalmente se considera una fuga “parásita” en una condición en la que, idealmente, no debería haber conducción. Por lo tanto, las actividades por debajo del umbral reducen el problema de disminuir el consumo de energía, pero lo hacen a expensas del deterioro del rendimiento del sistema, las fluctuaciones en la estabilidad y funcionalidad del sistema, las variaciones de temperatura y, lo que es más importante, la utilización del espacio de diseño. Para minimizar algunos de estos interruptores redundantes y hacer que los circuitos sean más eficientes desde el punto de vista energético manteniendo la funcionalidad, este estudio sugiere dos nuevas técnicas. Utiliza un método de optimización basado en cambiar el voltaje de umbral para reducir la energía de falla. Se crea una lista de conexiones de circuito impecable utilizando un algoritmo mientras se mantiene el rendimiento de retardo requerido. El uso de este enfoque da como resultado una reducción general del 6,14 % en el consumo de energía.O último século assistiu a uma evolução da tecnologia que melhorou os sistemas de comunicação e, em geral, facilitou a vida das pessoas. Nossos sistemas de comunicação tornaram-se mais rápidos e confiáveis como resultado da explosão de aparelhos e serviços. Mas, essas atualizações têm um preço. O consumo de energia é um dos custos mais preocupantes. Nos últimos anos, a solução envolveu a instalação de baterias maiores e mais potentes, desde que isso não limitasse a mobilidade. Os problemas econômicos e ambientais de hoje nos obrigam a considerar soluções alternativas, como métodos para reduzir o consumo de energia de dispositivos digitais. Este estudo se concentra no uso de circuitos digitais, que prometem oferecer boa eficiência energética e desempenho desejável com economia de tensão muito baixa. Certos interruptores digitais são supostamente redundantes e não são necessários para o funcionamento adequado do circuito, mas continuam a consumir energia. Portanto, um dos principais problemas para o projeto de baixo consumo de energia é reduzir esses switches redundantes. A condução abaixo do limiar em circuitos digitais é normalmente vista como uma fuga “parasita” em uma condição em que idealmente não deveria haver condução. As atividades abaixo do limite reduzem, assim, o problema de diminuir o consumo de energia, mas o fazem às custas da deterioração da taxa de transferência do sistema, flutuações na estabilidade e funcionalidade do sistema, variações de temperatura e, mais criticamente, utilização do espaço de projeto. A fim de minimizar alguns desses switches redundantes e tornar os circuitos mais eficientes em termos de energia, mantendo a funcionalidade, este estudo sugere duas novas técnicas. Ele usa um método de otimização baseado na mudança de tensão limite para reduzir a energia de falha. Uma netlist de circuito sem falhas é criada usando um algoritmo, mantendo o desempenho de atraso necessário. O uso dessa abordagem resulta em uma redução geral de 6,14% no consumo de energia

EFFICIENT HARDWARE PRIMITIVES FOR SECURING LIGHTWEIGHT SYSTEMS

In the era of IoT and ubiquitous computing, the collection and communication of sensitive data is increasingly being handled by lightweight Integrated Circuits. Efficient hardware implementations of crytographic primitives for resource constrained applications have become critical, especially block ciphers which perform fundamental operations such as encryption, decryption, and even hashing. We study the efficiency of block ciphers under different implementation styles. For low latency applications that use unrolled block cipher implementations, we design a glitch filter to reduce energy consumption. For lightweight applications, we design a novel architecture for the widely used AES cipher. The design eliminates inefficiencies in data movement and clock activity, thereby significantly improving energy efficiency over state-of-the-art architectures. Apart from efficiency, vulnerability to implementation attacks are a concern, which we mitigate by our randomization capable lightweight AES architecture. We fabricate our designs in a commercial 16nm FinFET technology and present measured testchip data on energy consumption and side channel resistance. Finally, we address the problem of supply chain security by using image processing techniques to extract fingerprints from surface texture of plastic IC packages for IC authentication and counterfeit prevention. Collectively these works present efficient and cost effective solutions to secure lightweight systems

Gate-level timing analysis and waveform evaluation

Static timing analysis (STA) is an integral part of modern VLSI chip design. Table lookup based methods are widely used in current industry due to its fast runtime and mature algorithms. Conventional STA algorithms based on table-lookup methods are developed under many assumptions in timing analysis; however, most of those assumptions, such as that input signals and output signals can be accurately modeled as ramp waveforms, are no longer satisfactory to meet the increasing demand of accuracy for new technologies. In this dissertation, we discuss several crucial issues that conventional STA has not taken into consideration, and propose new methods to handle these issues and show that new methods produce accurate results. In logic circuits, gates may have multiple inputs and signals can arrive at these inputs at different times and with different waveforms. Different arrival times and waveforms of signals can cause very different responses. However, multiple-input transition effects are totally overlooked by current STA tools. Using a conventional single-input transition model when multiple-input transition happens can cause significant estimation errors in timing analysis. Previous works on this issue focus on developing a complicated gate model to simulate the behavior of logic gates. These methods have high computational cost and have to make significant changes to the prevailing STA tools, and are thus not feasible in practice. This dissertation proposes a simplified gate model, uses transistor connection structures to capture the behavior of multiple-input transitions and requires no change to the current STA tools. Another issue with table lookup based methods is that the load of each gate in technology libraries is modeled as a single lumped capacitor. But in the real circuit, the Abstract 2 gate connects to its subsequent gates via metal wires. As the feature size of integrated circuit scales down, the interconnection cannot be seen as a simple capacitor since the resistive shielding effect will largely affect the equivalent capacitance seen from the gate. As the interconnection has numerous structures, tabulating the timing data for various interconnection structures is not feasible. In this dissertation, by using the concept of equivalent admittance, we reduce an arbitrary interconnection structure into an equivalent π-model RC circuit. Many previous works have mapped the π-model to an effective capacitor, which makes the table lookup based methods useful again. However, a capacitor cannot be equivalent to a π-model circuit, and will thus result in significant inaccuracy in waveform evaluation. In order to obtain an accurate waveform at gate output, a piecewise waveform evaluation method is proposed in this dissertation. Each part of the piecewise waveform is evaluated according to the gate characteristic and load structures. Another contribution of this dissertation research is a proposed equivalent waveform search method. The signal waveforms can be very complicated in the real circuits because of noises, race hazards, etc. The conventional STA only uses one attribute (i.e., transition time) to describe the waveform shape which can cause significant estimation errors. Our approach is to develop heuristic search functions to find equivalent ramps to approximate input waveforms. Here the transition time of a final ramp can be completely different from that of the original waveform, but we can get higher accuracy on output arrival time and transition time. All of the methods mentioned in this dissertation require no changes to the prevailing STA tools, and have been verified across different process technologies

A 12-bit pseudo-differential current-source resistor-string hybrid digital-to-analogue converter with low pass rc filter.

Major concern in a high speed digital to analogue converter (DAC) is the occurrence of glitches which limiting the performance of the converter. As technology moving toward higher speed and smaller sizes, eliminating glitches is very important to ensure maximum performance of a DAC. Glitches limit maximum performance of a DAC especially in term of switching speed where it restrict the high speed performance of DAC. In some cases glitches can cause the converter to be unusable. This work discusses the design methodology to further improve glitches in the existing hybrid DAC with current-limited swing reduced driver circuit. The 12 bit hybrid DAC architectures is composed of 8-LSB binary-weighted resistor and 4-MSB thermometer coding in order to have optimize performance. The improved DAC design is accomplished by incorporating a Low Pass RC filter which function to attenuate the amplitude of the glitch that exceed the cutoff frequency, Fc . Simulation results shows that glitch impulse area was 9.1046pVs while peak glitch is only 1.08mV. This results indicates that this design achieves 70% improvement in glitch impulse area reduction compared with original version DAC and showing improvement of 47.71% compared to DAC with only current limited SRD. Overall, this project have successfully achieves lower glitch impulse ar

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0µW/MHz versus 10.9µW/MHz and more for 0.25µm CMOS technology at 0.75V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55nW versus 0.84nW in CSM and 0.94nW in Wallace