An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement

The power mixer array is presented as a novel power generation approach for non-constant envelope signals. It comprises several power mixer units that are dynamically turned on and off to improve the linearity and back-off efficiency. At the circuit level, the power mixer unit can operate as a switching amplifier to achieve high peak power efficiency. Additional circuit level linearization and back-off efficiency improvement techniques are also proposed. To demonstrate the feasibility of this idea, a fully-integrated octave-range CMOS power mixer array is implemented in a 130 nm CMOS process. It is operational between 1.2 GHz and 2.4 GHz and can generate an output power of +31.3 dBm into an external 50 Ω load with a PAE of 42% and a gain compression of only 0.4 dB at 1.8 GHz. It achieves a PAE of 25%, at an average output power of +26.4 dBm, and an EVM of 4.6% with a non-constant-envelope 16 QAM signal. It can also produce arbitrary signal levels down to -70 dBm of output power with the 16 QAM-modulated signal without any RF gain control circuit

Pseudo noise code and data transmission method and apparatus

Pseudo noise ranging codes, having a predetermined chipping rate, and a pair of binary data sources, each having a bit rate no greater than one tenth the chipping rate, quadriphase, digitally modulate a suppressed carrier wave having a first frequency are examined. Two additional binary data sources, each having a bit rate that is not restricted by the chipping rate of the first carrier, quadriphase, digitally modulate a suppressed carrier wave having a second frequency. The first and second frequencies are only slightly displaced so that there is overlap in the frequency bands which modulate the two carriers. The two suppressed carrier waves are linearly combined and transmitted from a first station to a second station so that the amplitude of the transmitted first wave is controlled so as not to degrade the detectability of the second wave at the second station

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

What effect does network size have on NRTK positioning?

The Network Real Time Kinematic (NRTK) positioning is nowadays a very common practice not only in academia but also in the professional world. To support the users several networks of Continuous Operating Reference Stations (CORSs) were born. These networks offer real-time services for NRTK positioning, providing a centimetric positioning accuracy with an average distance of 25-35 kms between the reference stations. But what is the effective distance between reference stations that allows to achieve the precision required for real-time positioning, using both geodetic and GIS receivers? How the positional accuracy changes with increasing distances between CORS? Can a service of geostationary satellites, such as the European EGNOS, be an alternative to the network positioning for medium-low cost receivers? These are only some of the questions that the Authors try to answer in this articl

Composite CDMA - A statistical mechanics analysis

Code Division Multiple Access (CDMA) in which the spreading code assignment to users contains a random element has recently become a cornerstone of CDMA research. The random element in the construction is particular attractive as it provides robustness and flexibility in utilising multi-access channels, whilst not making significant sacrifices in terms of transmission power. Random codes are generated from some ensemble, here we consider the possibility of combining two standard paradigms, sparsely and densely spread codes, in a single composite code ensemble. The composite code analysis includes a replica symmetric calculation of performance in the large system limit, and investigation of finite systems through a composite belief propagation algorithm. A variety of codes are examined with a focus on the high multi-access interference regime. In both the large size limit and finite systems we demonstrate scenarios in which the composite code has typical performance exceeding sparse and dense codes at equivalent signal to noise ratio.Comment: 23 pages, 11 figures, Sigma Phi 2008 conference submission - submitted to J.Stat.Mec