Voltage-induced strain clocking of nanomagnets with perpendicular magnetic anisotropies

Nanomagnetic logic (NML) has attracted attention during the last two decades due to its promise of high energy efficiency combined with non-volatility. Data transmission in NML relies on Bennett clocking through dipole interaction between neighboring nanomagnetic bits. This paper uses a fully coupled finite element model to simulate Bennett clocking based on strain-mediated multiferroic system for Ni, CoFeB and Terfenol-D with perpendicular magnetic anisotropies. Simulation results demonstrate that Terfenol-D system has the highest energy efficiency, which is 2 orders of magnitude more efficient than Ni and CoFeB. However, the high efficiency is associated with switching incoherency due to its large magnetostriction coefficient. It is also suggested that the CoFeB clocking system is slower and has lower bit-density than in Ni or Terfenol-D systems due to its large dipole coupling. Moreover, we demonstrate that the precessional perpendicular switching and the Bennett clocking can be achieved using the same strain-mediated multiferroic architecture with different voltage pulsing. This study opens new possibilities to an all-spin in-memory computing system

Noise-assisted Multibit Storage Device

In this paper we extend our investigations on noise-assisted storage devices through the experimental study of a loop composed of a single Schmitt trigger and an element that introduces a finite delay. We show that such a system allows the storage of several bits and does so more efficiently for an intermediate range of noise intensities. Finally, we study the probability of erroneous information retrieval as a function of elapsed time and show a way for predicting device performance independently of the number of stored bits.Comment: 5 figure

Reverse Connection of MTJ Device in STT-RAM Cell

STT-RAM technology is an emerging memory technology which is a future replacement for conventional memory technologies. STT-RAM promises fast read-write-access speeds, low power consumption, high density, non-volatility and very long life time. As with any emerging technology, however, STT-RAM has its own set of characteristic disadvantages which must first be overcome before it can be considered a viable replacement for existing solutions, an example of such being its asymmetric behavior during write operations. Currently, reverse connection of the MTJ device in STT-RAM cells is being proposed as a novel solution for compensating for this asymmetric write operation. In this work, two different MTJ devices are examined to determine which one is better suited for use with conventional connection method and which is more convenient to use with the proposed reverse connection method. Thereafter, the results of the study are applied to determine what properties of an MTJ device most heavily influence whether it is best utilized with a reverse connection versus a conventional connection

From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula

© 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions. As the typical feature size of CMOS VLSI is shrunk into deep submicron domain, nanotechnology is the next step in order to maintain Moore’s law for several more decades. Nanotechnology not only further improves the resolution in traditional photolithography process, but also introduces many brand-new fabrication strategies, such as bottom-up molecular self-assembly. Nanotechnology is also enabling many novel devices and circuit architectures which are totally different from current microelectronics circuits, such as quantum computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is bringing another technology revolution to traditional CMOS VLSI technology. In order to train students to meet the quickly-increasing industry demand for nextgeneration nanoelectronics engineers, we are making efforts to introduce nanotechnology into our VLSI curricula. We have developed a series of VLSI curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing, etc. Furthermore, we developed a series of micro and nanotechnology related courses, such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 – MEMS (Microelectromechanical Systems). We introduce nanotechnology into our VLSI curricula, and teach the students about various devices, fabrication processes, circuit architectures, design and simulation skills for future nanotechnology-based nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture, carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum computing, bioelectronic circuits, etc. Students show intense interest in these exciting topics. Some students also choose nanoelectronics as the topic for their master project/thesis, and perform successful research in the field. The program has attracted many graduate students into the field of nanoelectronics