Command list (Array A-2)

This command list applies to Array A-Z. Command lists for Arrays A, B and C (Flight Systems 1, 3, 4) are given in ATM-369 and the command list for Array D is given in ATM-872. This ATM also summarizes and collates the command usage for the Arrays A, B, C, A-Z and D

On the importance of nonlinear modeling in computer performance prediction

Computers are nonlinear dynamical systems that exhibit complex and sometimes even chaotic behavior. The models used in the computer systems community, however, are linear. This paper is an exploration of that disconnect: when linear models are adequate for predicting computer performance and when they are not. Specifically, we build linear and nonlinear models of the processor load of an Intel i7-based computer as it executes a range of different programs. We then use those models to predict the processor loads forward in time and compare those forecasts to the true continuations of the time seriesComment: Appeared in "Proceedings of the 12th International Symposium on Intelligent Data Analysis

The SIFT hardware/software systems. Volume 1: A detailed description

This report contains a detailed description of the software implemented fault-tolerant computer's operating system and hardware subsystems. The Software Implemented Fault-Tolerant (SIFT) computer system was developed as an experimental vehicle for fault-tolerant systems research. The SIFT effort began with broad, in-depth studies stating the reliability and processing requirements for digital computers which would, in the aircraft of the 1990's, control flight-critical functions

Motorcycle Helmet Crash Detection/Prevention System

This project proposes a motorcycle safety system that increases safety by actively helping to prevent crashes while also helping in the case that an accident does occur. The system actively helps prevent accidents by keeping the user’s eyes on the road with three additions to the typical helmet. The helmet has a heads-up-display (HUD) containing the speed of the motorcycle and turn-by-turn directions. Instead of tilting their head down the user can see their speed and directions by moving their eyes which will keep the road in their field of view. Blind-spot detection increases the user’s overall awareness of their surroundings. The helmet increases the speed of response when an emergency situation occurs. After a crash has been detected, emergency response will be notified via call and text from the user’s phone. In order to increase attention to the accident, external LEDs flash and an external speaker sounds. Keeping the driver’s eyes on the road makes for a safer driving experience which decreases the number of crashes. Having emergency response arrive quicker helps to improve the chances of a speedy recovery or even could save a person’s life

UC: a language for the connection machine

n designing parallel languages, the concern for defining a simple virtual machine must be balanced against the need to efficiently map a program on a specific architecture. UC addresses this problem by separating the programming task from efficiency considerations. UC programs are designed using a small set of constructs that include reduction, parallel assignment, and fixed-point computation. The language also provides a map section that may optionally be used by a programmer to specify data mappings for the program. The authors describe the UC constructs and their implementation on the Connection Machine. They also present measurements of the compiler for simple benchmarks

Parallelization of the H.261 video coding algorithm on the IBM SP2(R) multiprocessor system

In this paper, the parallelization of the H.261 video coding algorithm on the IBM SP2 multiprocessor system is described. Based on domain decomposition as a framework, data partitioning, data dependencies and communication issues are carefully assessed. From these, two parallel algorithms were developed with the first one maximizes on processor utilization and the second one minimizes on communications. Our analysiis shows that the first algorithm exhibits poor scalability and high communication overhead; and the second algorithm exhibits good scalability and low communication overhead. A best median speed up of 13.72 or 11 frameskec was achieved on 24 processors.published_or_final_versio

Scalable Parallel Computers for Real-Time Signal Processing

We assess the state-of-the-art technology in massively parallel processors (MPPs) and their variations in different architectural platforms. Architectural and programming issues are identified in using MPPs for time-critical applications such as adaptive radar signal processing. We review the enabling technologies. These include high-performance CPU chips and system interconnects, distributed memory architectures, and various latency hiding mechanisms. We characterize the concept of scalability in three areas: resources, applications, and technology. Scalable performance attributes are analytically defined. Then we compare MPPs with symmetric multiprocessors (SMPs) and clusters of workstations (COWs). The purpose is to reveal their capabilities, limits, and effectiveness in signal processing. We evaluate the IBM SP2 at MHPCC, the Intel Paragon at SDSC, the Gray T3D at Gray Eagan Center, and the Gray T3E and ASCI TeraFLOP system proposed by Intel. On the software and programming side, we evaluate existing parallel programming environments, including the models, languages, compilers, software tools, and operating systems. Some guidelines for program parallelization are provided. We examine data-parallel, shared-variable, message-passing, and implicit programming models. Communication functions and their performance overhead are discussed. Available software tools and communication libraries are also introducedpublished_or_final_versio

Profiling I/O interrupts in modern architectures

Journal ArticleAs applications grow increasingly communication-oriented, interrupt performance quickly becomes a crucial component of high performance I/O system design. At the same time, accurately measuring interrupt handler performance is difficult with the traditional simulation, instrumentation, or statistical sampling approaches. One o f the most important components o f interrupt performance is cache behavior. This paper presents a portable method for measuring the cache effects o f I/O interrupt handling using native hardware performance counters. To provide a portability stress test, the method is demonstrated on two commercial platforms with different architectures, the SGI Origin 200 and the Sun LJltra-1. This case study uses the methodology to measure the overhead of the two most common forms o f interrupt traffic: disk and network interrupts. The study demonstrates that the method works well and is reasonably robust. In addition, the results show that disk interrupts behave similar on both platforms, while differences in OS organization cause network interrupts to behave very differently. Furthermore, network interrupts exhibit significantly larger cache footprints.

Practical realisation and elimination of an ECC-related software bug attack

We analyse and exploit implementation features in OpenSSL version 0.9.8g which permit an attack against ECDH-based functionality. The attack, although more general, can recover the entire (static) private key from an associated SSL server via $633$ adaptive queries when the NIST curve P-256 is used. One can view it as a software-oriented analogue of the bug attack concept due to Biham et al. and, consequently, as the first bug attack to be successfully applied against a real-world system. In addition to the attack and a posteriori countermeasures, we show that formal verification, while rarely used at present, is a viable means of detecting the features which the attack hinges on. Based on the security implications of the attack and the extra justification posed by the possibility of intentionally incorrect implementations in collaborative software development, we conclude that applying and extending the coverage of formal verification to augment existing test strategies for OpenSSL-like software should be deemed a worthwhile, long-term challenge.This work has been supported in part by EPSRC via grant EP/H001689/1 and by project SMART, funded by ENIAC Joint Undertaking (GA 120224)