Decomposition of network of queues with self-similar traffic

Jackson's network of queues model greatly simplifies the performance analysis of telecommunication networks with Poisson traffic arrivals and exponential service times. It reduces the analysis of a network into the analysis of individual communication links, each of which may be modeled as an M/M/m queue. Motivated by the growing significance of self-similar traffic in modeling broadband network traffic, we propose a new network of queues model for telecommunication networks. Our model resembles Jackson's model except that the arrival is self-similar and the service time is deterministic. It captures the characteristics of modern high speed cell-based networks. We hypothesize a result analogous to Jackson's Theorem, that each mode of this network model behaves as a G/D/1 queue with self-similar arrival. Based on this hypothesis, many network-wide performance measures, such as the end-to-end delay, can be evaluated in a simple fashion. Our hypothesis is strongly supported by three facts, namely, the sum of independent self-similar processes, the random splitting of self-similar processes, and the output process of a deterministic service time queue with self-similar input are all self-similar.published_or_final_versio

Decomposition of network of queues with self-similar traffic

Jackson's network of queues model greatly simplifies the performance analysis of telecommunication networks with Poisson traffic arrivals and exponential service times. It reduces the analysis of a network into the analysis of individual communication links, each of which may be modeled as an M/M/m queue. Motivated by the growing significance of self-similar traffic in modeling broadband network traffic, we propose a new network of queues model for telecommunication networks. Our model resembles Jackson's model except that the arrival is self-similar and the service time is deterministic. It captures the characteristics of modern high speed cell-based networks. We hypothesize a result analogous to Jackson's Theorem, that each mode of this network model behaves as a G/D/1 queue with self-similar arrival. Based on this hypothesis, many network-wide performance measures, such as the end-to-end delay, can be evaluated in a simple fashion. Our hypothesis is strongly supported by three facts, namely, the sum of independent self-similar processes, the random splitting of self-similar processes, and the output process of a deterministic service time queue with self-similar input are all self-similar.published_or_final_versio

Utilizing Magnetic Tunnel Junction Devices in Digital Systems

The research described in this dissertation is motivated by the desire to effectively utilize magnetic tunnel junctions (MTJs) in digital systems. We explore two aspects of this: (1) a read circuit useful for global clocking and magnetologic, and (2) hardware virtualization that utilizes the deeply-pipelined nature of magnetologic. In the first aspect, a read circuit is used to sense the state of an MTJ (low or high resistance) and produce a logic output that represents this state. With global clocking, an external magnetic field combined with on-chip MTJs is used as an alternative mechanism for distributing the clock signal across the chip. With magnetologic, logic is evaluated with MTJs that must be sensed by a read circuit and used to drive downstream logic. For these two uses, we develop a resistance-to-voltage (R2V) read circuit to sense MTJ resistance and produce a logic voltage output. We design and fabricate a prototype test chip in the 3 metal 2 poly 0.5 um process for testing the R2V read circuit and experimentally validating its correctness. Using a clocked low/high resistor pair, we show that the read circuit can correctly detect the input resistance and produce the desired square wave output. The read circuit speed is measured to operate correctly up to 48 MHz. The input node is relatively insensitive to node capacitance and can handle up to 10s of pF of capacitance without changing the bandwidth of the circuit. In the second aspect, hardware virtualization is a technique by which deeply-pipelined circuits that have feedback can be utilized. MTJs have the potential to act as state in a magnetologic circuit which may result in a deep pipeline. Streams of computation are then context switched into the hardware logic, allowing them to share hardware resources and more fully utilize the pipeline stages of the logic. While applicable to magnetologic using MTJs, virtualization is also applicable to traditional logic technologies like CMOS. Our investigation targets MTJs, FPGAs, and ASICs. We develop M/D/1 and M/G/1 queueing models of the performance of virtualized hardware with secondary memory using a fixed, hierarchical, round-robin schedule that predict average throughput, latency, and queue occupancy in the system. We develop three C-slow applications and calibrate them to a clock and resource model for FPGA and ASIC technologies. Last, using the M/G/1 model, we predict throughput, latency, and resource usage for MTJ, FPGA, and ASIC technologies. We show three design scenarios illustrating ways in which to use the model