FPGA-accelerated group-by aggregation using synchronizing caches

Recent trends in hardware have dramatically dropped the price of RAM and shifted focus from systems operating on disk-resident data to in-memory solutions. In this environment high memory access latency, also known as memory wall, becomes the biggest data processing bottleneck. Traditional CPU-based architectures solved this problem by introducing large cache hierarchies. However algorithms which experience poor locality can limit the benefits of caching. In turn, hardware multithreading provides a generic solution that does not rely on algorithm-specific locality properties. In this paper we present an FPGA-accelerated implementation of in-memory group-by hash aggregation. Our design relies on hardware multithreading to efficiently mask long memory access latency by implementing a custom operation datapath on FPGA. We propose using CAMs (Content Addressable Memories) as a mechanism of synchronization and local pre-aggregation. To the best of our knowledge this is the first work, which uses CAMs as a synchronizing cache. We evaluate aggregation throughput against the state-of-the-art multithreaded software implementations and demonstrate that the FPGA-accelerated approach significantly outperforms them on large grouping key cardinalities and yields speedup up to 10x

DRAM Aware Last-Level-Cache Policies for Multi-core Systems

Two important parameters for DRAM cache are the miss rate and the hit latency, as they strongly influence the performance. This thesis investigate the latency and miss rate trade-offs when designing a DRAM cache hierarchy. It proposes novel application-aware and DRAM aware policies that simultaneously reduce miss rate (while considering the cache access pattern of concurrently running applications) and hit latency (while considering DRAM characteristics)