An Effective Satellite Remote Sensing Tool Combining Hardware and Software Solutions

In this paper we propose a new effective remote sensing tool combining hardware and software solutions as an extension of our previous work. In greater detail the tool consists of a low cost receiver subsystem for public weather satellites and a signal and image processing module for several tasks such as signal and image enhancement, image reconstruction and cloud detection. Our solution allows to manage data from satellites effectively with low cost components and portable software solutions. We aim at sampling and processing of the modulated signal entirely in software enabled by Software Defined Radios (SDR) and CPU computational speed overcoming hardware limitation such as high receiver noise and low ADC resolution. Since we want to extend our previous method to demodulate signals coming from various meteorological satellites, we propose a new high frequency receiving system designed to receive and demodulate signals transmitted at 1.7 GHz. The signals coming from satellites are demodulated, synchronized and enhanced by using low level image processing techniques, then cloud detection is performed by using the well known K-means clustering algorithm. The hardware and software architecture extensions make our solution able to receive and demodulate high frequency and bandwidth meteorological satellite signals, such as those transmitted by NOAA POES, NOAA GOES, EUMETSAT Metop, Meteor-M and FengYun

Accelerating Halide on an FPGA by using CIRCT and Calyx as an intermediate step to go from a high-level and software-centric IRs down to RTL

Image processing and, more generally, array processing play an essential role in modern life: from applying filters to the images that we upload to social media to running object detection algorithms on self-driving cars. Optimizing these algorithms can be complex and often results in non-portable code. The Halide language provides a simple way to write image and array processing algorithms by separating the algorithm definition (what needs to be executed) from its execution schedule (how it is executed), delivering state-of-the-art performance that exceeds hand-tuned parallel and vectorized code. Due to the inherent parallel nature of these algorithms, FPGAs present an attractive acceleration platform. While previous work has added an RTL code generator to Halide, and utilized other heterogeneous computing languages as an intermediate step, these projects are no longer maintained. MLIR is an attractive solution, allowing the generation of code that can target multiple devices, such as parallelized and vectorized CPU code, OpenMP, and CUDA. CIRCT builds on top of MLIR to convert generic MLIR code to register transfer level (RTL) languages by using Calyx, a new intermediate language (IL) for compiling high-level programs into hardware designs. This thesis presents a novel flow that implements an MLIR code generator for Halide that generates RTL code, adding the necessary wrappers to execute that code on Xilinx FPGA devices. Additionally, it implements a Halide runtime using the Xilinx Runtime (XRT), enabling seamless execution of the generated Halide RTL kernels. While this thesis provides initial support for running Halide kernels and not all features and optimizations are supported, it also details the future work needed to improve the performance of the generated RTL kernels. The proposed flow serves as a foundation for further research and development in the field of hardware acceleration for image and array processing applications using Halide

Low-Complexity Hyperspectral Image Compression on a Multi-tiled Architecture

The increasing amount of data produced in satellites poses a downlink communication problem due to the limited data rate of the downlink. This bottleneck is solved by introducing more and more processing power on-board to compress data to a satisfiable rate. Currently, this processing power is often provided by custom off the shelf hardware which is needed to run the complex image compression standards. The increase in required processing power often increases the energy required to power the hardware. This in turn pushes algorithm developers to develop lower complexity algorithms which are able to compress the data for the least amount of processing per data element. On the other hand hardware developers are pushed to develop flexible hardware which can be used on multiple missions to cut development cost and can be re-used for different missions. This paper introduces an algorithm which has been developed\ud to compress hyperspectral images at low complexity and describes its mapping to a new hardware platform which has been developed to offer flexibility as well as high performance processing power called the Xentium tile processor

Towards a Scalable Hardware/Software Co-Design Platform for Real-time Pedestrian Tracking Based on a ZYNQ-7000 Device

Currently, most designers face a daunting task to research different design flows and learn the intricacies of specific software from various manufacturers in hardware/software co-design. An urgent need of creating a scalable hardware/software co-design platform has become a key strategic element for developing hardware/software integrated systems. In this paper, we propose a new design flow for building a scalable co-design platform on FPGA-based system-on-chip. We employ an integrated approach to implement a histogram oriented gradients (HOG) and a support vector machine (SVM) classification on a programmable device for pedestrian tracking. Not only was hardware resource analysis reported, but the precision and success rates of pedestrian tracking on nine open access image data sets are also analysed. Finally, our proposed design flow can be used for any real-time image processingrelated products on programmable ZYNQ-based embedded systems, which benefits from a reduced design time and provide a scalable solution for embedded image processing products

How to find real-world applications for compressive sensing

The potential of compressive sensing (CS) has spurred great interest in the research community and is a fast growing area of research. However, research translating CS theory into practical hardware and demonstrating clear and significant benefits with this hardware over current, conventional imaging techniques has been limited. This article helps researchers to find those niche applications where the CS approach provides substantial gain over conventional approaches by articulating lessons learned in finding one such application; sea skimming missile detection. As a proof of concept, it is demonstrated that a simplified CS missile detection architecture and algorithm provides comparable results to the conventional imaging approach but using a smaller FPA. The primary message is that all of the excitement surrounding CS is necessary and appropriate for encouraging our creativity but we all must also take off our "rose colored glasses" and critically judge our ideas, methods and results relative to conventional imaging approaches.Comment: 10 page

An Efficient and Cost Effective FPGA Based Implementation of the Viola-Jones Face Detection Algorithm

We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping