Modeling, Synthesis, and Validation of Heterogeneous Biomedical Embedded Systems

Abstract-The increasing performance and availability of embedded systems increases their attractiveness for biomedical applications. With advances in sensor processing and classification algorithms, real-time decision support in patient monitoring becomes feasible. However, the gap between algorithm design and their embedded realization is growing. This paper overviews an approach for development of biomedical devices at an abstract algorithm level with automatic generation of an embedded implementation. Based on a case study of a Brain Computer Interface (BCI), this paper demonstrates capturing, modeling and synthesis of such applications

Modelling SystemC scheduler by refinement

Systems on Chip, or shortly SoCs, and SoC architectures denote a challenging set of problems of specification, modelling techniques, security issues and structuring questions. Our methodology, for designing models of (SoC) system from requirements, leads to formally justify hints on the future architectural choices of that system; it is based on the B event-based method, which integrates the incremental development of models using a theorem prover to validate each step of development called refinement. The target system is generally expressed using a programming language notation like SystemC; the SystemC language is used by electronic designers to describe different parts of the system (hardware and software); SystemC constitutes a general framework for simulating and validating the design of the system under construction. The semantics of SystemC is based on its scheduling algorithm described in the language reference manual and we develop a B model of the scheduling. The B \textit{scheduling} model left unspecified parameters depending on the simulated SystemC program and those parameters are instantiated from the operational semantics of the developed SystemC program. By instantiation, we obtain a B abstract model of the simulated program and we can study properties of the SystemC program by simulation. B models are completely validated by the proof assistant of the event-B method. Finally, our models provide a sound framework for understanding the scheduling process

Implementação de modelos de redes de Petri em hardware de lógica reconfigurável

In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um software de captura onde, a partir do gráfico do modelo em Rede de Petri, é gerado um arquivo de descrição no formato PNML - Linguagem de Marcação para Rede de Petri (Petri Net Markup Language). A partir desta descrição, é gerado um arquivo de descrição de hardware no formato VHDL - Linguagem de Descrição de Hardware VHSIC (VHSIC Hardware Description Language), que pode ser gravado em um circuito de lógica reconfigurável. Para possibilitar esta etapa, foi realizado o desenvolvimento de uma ferramenta que gera um arquivo em linguagem VHDL a partir da descrição no formato PNML. A ferramenta desenvolvida é descrita em detalhes, mostrando todas as etapas e critérios utilizados na conversão. Para validar o método, é mostrado um exemplo de aplicação com a implementação em FPGA - Matriz de Portas Programável em Campo (Field Programmable Gate Arrow), de uma Rede de Petri modelando uma planta industrial hipotética. Finalmente é feita uma comparação de desempenho entre o modelo executado em hardware com o modelo executado em software

IEEE/NASA Workshop on Leveraging Applications of Formal Methods, Verification, and Validation

This volume contains the Preliminary Proceedings of the 2005 IEEE ISoLA Workshop on Leveraging Applications of Formal Methods, Verification, and Validation, with a special track on the theme of Formal Methods in Human and Robotic Space Exploration. The workshop was held on 23-24 September 2005 at the Loyola College Graduate Center, Columbia, MD, USA. The idea behind the Workshop arose from the experience and feedback of ISoLA 2004, the 1st International Symposium on Leveraging Applications of Formal Methods held in Paphos (Cyprus) last October-November. ISoLA 2004 served the need of providing a forum for developers, users, and researchers to discuss issues related to the adoption and use of rigorous tools and methods for the specification, analysis, verification, certification, construction, test, and maintenance of systems from the point of view of their different application domains

The formal execution semantics of SpecC

We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, waitfor, par, pipe, and try statements as they are introduced in SpecC. We present our definition in form of distributed Abstract State Machine (ASM) rules reflecting the specification given in the SpecC Language Reference Manual [5]. We mainly see our formal semantics in three application areas. First, it can be taken as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator which is outlined in a separate section. Second, it is a concise, unambiguous description for documentation and standardization. Finally, it is a first step for Spece synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets

The Formal Execution Semantics of SpecC

... State Machine (ASM) rules reflecting the specification given in the SpecC Language Reference Manual [5]. We mainly see our formal semantics in three application areas. First, it can be taken as a high--level, pseudo code--oriented specification for the implementation of a SpecC simulator which is outlined in a separate section. Second, it is a concise, unambiguous description for documentation and standardization. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets