An all-silicon single-photon source by unconventional photon blockade

The lack of suitable quantum emitters in silicon and silicon-based materials has prevented the realization of room temperature, compact, stable, and integrated sources of single photons in a scalable on-chip architecture, so far. Current approaches rely on exploiting the enhanced optical nonlinearity of silicon through light confinement or slow-light propagation, and are based on parametric processes that typically require substantial input energy and spatial footprint to reach a reasonable output yield. Here we propose an alternative all-silicon device that employs a different paradigm, namely the interplay between quantum interference and the third-order intrinsic nonlinearity in a system of two coupled optical cavities. This unconventional photon blockade allows to produce antibunched radiation at extremely low input powers. We demonstrate a reliable protocol to operate this mechanism under pulsed optical excitation, as required for device applications, thus implementing a true single-photon source. We finally propose a state-of-art implementation in a standard silicon-based photonic crystal integrated circuit that outperforms existing parametric devices either in input power or footprint area.Comment: 5 pages, 3 figures + Supplementary information (3 pages, 2 figures

Data encryption standard simulation and a bit-slice architecture design

This paper presents a high level language implementation of the Data Encryption Standard (DES) and discusses a design that employs a bit-sliced architecture. The HLL implementation was performed on Borland's® Delphi4™, language and proved to be highly valuable for obtaining the intermediate results that were required for debugging. The key objectives of this work were to make DES available for system applications written in the Delphi4 TM language and also to discuss the design of a bit-sliced DES architecture suitable for applications requiring low silicon area

Parallel asynchronous systems and image processing algorithms

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science

Real-Time Displaying Quality Maps of Silicon Wafers

Cílem této bakalářské práce je navrhnout a implementovat softwarový systém, který dokáže v reálném čase sbírat data z průběhů měření křemíkových plátů. Může se jednat o desítky až stovky měření a data z těchto měření jsou uživatelům vykreslována (taktéž v reálném čase). Práce obsahuje popis procesu výroby a testování integrovaných obvodů. Následně pak návrh architektury systému aplikací, vnitřní architektury serveru a grafického uživatelského rozhraní klientské aplikace. V poslední části je ukázáno, jakým způsobem bylo implementováno vykreslování křemíkových plátů na platformě JavaFX 2.2 a hybridní vícevláknová architektura serveru.The goal of this bachelor's thesis is to design and implement a software system that can collect real-time data from measurements of silicon wafers. There could be tens or hundreds data sources of measurements and data from these measurements can be rendered (also in real time). This work contains a description of the process of manufacturing and testing of integrated circuits. Subsequently, there is description of system architecture design, interior architecture of real-time server and GUI of client application. In the last section, there is shown how rendering of silicon wafers was implemented on platform JavaFX 2.2 and also implementation of hybrid multi-threading server architecture.

Scalable and high-sensitivity readout of silicon quantum devices

Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems

GaAs Implementation of FIR Filter

This thesis discusses the findings of the final year project involving Gallium Arsenide implementation of a triangular FIR filter to perform discrete wavelet transforms. The overall characteristics of Gallium Arsenide technology- its construction, behaviour and electrical charactersitics as they apply to VLSI technology - were investigated in this project. In depth understanding of its architecture is required to be able to understand the various design techniques employed. A comparison of Silicon and GaAs performance and other characteristics has also been made to fully justify the choice of this material for system implementation. A lot of research and active interest has gone into the field of image and video compression. Wavelet-based image transformation is one of the very efficient compression techniques used. An analysis of discrete wavelet transformations and the required triangular FIR filter was done to be able to produce a transform algorithm and the related filter architecture. Finally, the filter architecture was implemented as a VLSI design and layout. A variety of functional blocks required for the architecture were designed, tested and analysed. All these blocks were integrated to produce a model of a complete filter cell. The filter implementation was designed to be self-timed - without a system clock. Self-timed systems have considerable advantages over clocked architectures. Various design styles and handshaking mechanisms involved in designing a self-timed system were analysed and designed. There are many avenues still to explore. One of them is the VHDL analysis of filter architecture. Further development on this project would involve integration of higher-level logic and formation of a complete filter array

Pond: A Robust, scalable, massively parallel computer architecture

A new computer architecture, intended for implementation in late and post silicon technologies, is proposed. The architecture is a fine-grained, inherently parallel system consisting of a large grid of thousands or millions of simple atomic processors (APs) employing a simple instruction set. Each AP is configured as either a program instruction or data storage element. These elements are organized into logical entities, analogous to traditional programming functions/methods and data structures. Programming work is underway to compile and run programs from traditional sequential code where parallelism is automatically discovered at the high level on both instruction level and function level, and integrated into the object code that is then sent to the processor. The result is a massively parallel architecture that fully exploits instruction and thread-level parallelism. The architecture design is presented, in-progress work involving conversion of existing code is discussed, and examples are shown to indicate the speedup potential that exists in this new architecture when compared to current architectures