1,479 research outputs found
A Compact CMOS Memristor Emulator Circuit and its Applications
Conceptual memristors have recently gathered wider interest due to their
diverse application in non-von Neumann computing, machine learning,
neuromorphic computing, and chaotic circuits. We introduce a compact CMOS
circuit that emulates idealized memristor characteristics and can bridge the
gap between concepts to chip-scale realization by transcending device
challenges. The CMOS memristor circuit embodies a two-terminal variable
resistor whose resistance is controlled by the voltage applied across its
terminals. The memristor 'state' is held in a capacitor that controls the
resistor value. This work presents the design and simulation of the memristor
emulation circuit, and applies it to a memcomputing application of maze solving
using analog parallelism. Furthermore, the memristor emulator circuit can be
designed and fabricated using standard commercial CMOS technologies and opens
doors to interesting applications in neuromorphic and machine learning
circuits.Comment: Submitted to International Symposium of Circuits and Systems (ISCAS)
201
Multiplicador analógico CMOS baseado na relação transcondutância X corrente
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaO presente trabalho propõe um multiplicador operando em quarto quadrantes baseado em células que exploram a relação existente entre a corrente de saturação de um transistor MOS e a transcondutância de fonte. A vantagem da topologia proposta é simplicidade, operação com baixa potência, alta linearidade e corrente de saída com baixa sensibilidade dentro de uma mesma geração tecnológica. Os resultados de simulação associados aos experimentais demonstram a viabilidade da topologia escolhida para operação em baixa potência e baixa-tensão. A funcionalidade do sistema foi verificada através de simulação e da extração de parâmetros do protótipo implementado em tecnologia TSMC 0.35 m. Os resultados experimentais conseguidos com o protótipo indicam consumo de 1 mA, largura de banda de 1MHz e distorção harmônica total de 1% para uma corrente de entrada de 80 % do seu valor máximo sendo que a área de silício ocupada pelo multiplicador foi ao redor de 10.000 m2
CMOS analog-digital circuit components for low power applications
Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction
circuits for energy harvester.
The main contribution of this work is the realization of low power consumption and
high efficient circuit components employable in a management circuit for piezoelectricbased
energy harvester. This thesis focuses on the development of current references and
operational amplifiers addressing low power demands. A brief literature review is conducted
on the components necessary for the power extraction circuit, including introduction to
CMOS technology design and research of known low power circuits. It is presented with
multiple implementations for voltage and current references, as well for operational amplifier
designs.
A self-biased current reference, capable of driving the remaining harvesting circuit, is
designed and verified. A novel operational amplifier is proposed by the use of a minimum
current selector circuit topology. It is a three-stage amplifier with an AB class output stage,
comprised by a translinear circuit. The circuit is designed, taking into consideration noise
reduction. The circuit components are designed based on the 0.35mm CMOS technology.
A physical layout is developed for fabrication purposes. This technology was chosen with
consideration of robustness, costliness and performance. The current reference is capable of
outputting a stable 12nA current, which may remain stable in a broad range of power supply
voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at
voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW,
with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de
muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração
de energia com base num elemento piezoelétrico.
Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um
amplificador operacional com baixa exigência de consumo. Uma revisão da literatura
é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor
(CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações
de referência de tensão e corrente são consideradas, e amplificadores operacionais também.
Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e
verificada. Um amplificador operacional original é proposto com uma topologia de seleção
de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída
de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na
sua implementação.
Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi
também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em
conta o seu custo versus desempenho.
A referência de corrente produz uma corrente de 12nA, permanecendo estável para
tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um
coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de
alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima
mantida no estágio de saída
MOSFET ZTC condition analysis for a self-biased current reference design
In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
Semiconductor Device Modeling and Simulation for Electronic Circuit Design
This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions
Experimental Study and Modeling of the g\u3csub\u3em\u3c/sub\u3e-I Dependence of Long-Channel MOSFETs
This paper describes an experimental study and modeling of the current-transconductance dependence of the ALD1106 and ALD1107 arrays. The study tests the hypothesis that the I-g m dependence of these 7.8 μm MOSFETs conforms to the Advanced Compact Model (ACM). Results from performed measurements, however, do not support this expectation. Despite the relatively large length, both ALD1106 and ALD1107 show sufficiently pronounced `short-channel\u27 effects to render the ACM inadequate. As a byproduct of this effort, we confirmed the modified ACM equation. With an m factor of approximately 0.6, it captures the I-g m dependence quite well. The paper also introduces several formulas and procedures for I-g m model extraction and tuning. These are not specific to the ALD transistor family and can be applied to MOSFETs with different physical size and electrical performance
A behavioral model for the non-linear on-resistance in sample-and-hold analog switches
Abstract — This paper presents a behavioral model of the non-linear on-resistance in S&H analog switches. The model is suitable for analysis and design of low-voltage sampled data systems. Simulated results using the ATMEL 0.24µm CMOS process are shown to validate the model. The Advanced-Compact-Mosfet model (ACM), a symmetric drainto-source model, valid in the whole inversion level regime of MOS transistors, is used as reference.
Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation
This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated
- …