The Influence of Electron Beam Sterilization on In Vivo Degradation of β-TCP/PCL of Different Composite Ratios for Bone Tissue Engineering.

We evaluated the effect of electron beam (E-beam) sterilization (25 kGy, ISO 11137) on the degradation of β-tricalcium phosphate/polycaprolactone (β-TCP/PCL) composite filaments of various ratios (0:100, 20:80, 40:60, and 60:40 TCP:PCL by mass) in a rat subcutaneous model for 24 weeks. Volumes of the samples before implantation and after explantation were measured using micro-computed tomography (micro-CT). The filament volume changes before sacrifice were also measured using a live micro-CT. In our micro-CT analyses, there was no significant difference in volume change between the E-beam treated groups and non-E-beam treated groups of the same β-TCP to PCL ratios, except for the 0% β-TCP group. However, the average volume reduction differences between the E-beam and non-E-beam groups in the same-ratio samples were 0.76% (0% TCP), 3.30% (20% TCP), 4.65% (40% TCP), and 3.67% (60% TCP). The E-beam samples generally had more volume reduction in all experimental groups. Therefore, E-beam treatment may accelerate degradation. In our live micro-CT analyses, most volume reduction arose in the first four weeks after implantation and slowed between 4 and 20 weeks in all groups. E-beam groups showed greater volume reduction at every time point, which is consistent with the results by micro-CT analysis. Histology results suggest the biocompatibility of TCP/PCL composite filaments

Computer-Aided Test Flow in Core-Based Design

This paper copes with the test-pattern generation and fault coverage determination in the core based design. The basic core-test strategy that one has to apply in the core-based design is stated in this work. A Computer-Aided Test (CAT) flow is proposed resulting in accurate fault coverage of embedded cores. The CAT now is applied to a few cores within the Philips Core Test Pilot IC projec

Towards Vulnerability Discovery Using Staged Program Analysis

Eliminating vulnerabilities from low-level code is vital for securing software. Static analysis is a promising approach for discovering vulnerabilities since it can provide developers early feedback on the code they write. But, it presents multiple challenges not the least of which is understanding what makes a bug exploitable and conveying this information to the developer. In this paper, we present the design and implementation of a practical vulnerability assessment framework, called Melange. Melange performs data and control flow analysis to diagnose potential security bugs, and outputs well-formatted bug reports that help developers understand and fix security bugs. Based on the intuition that real-world vulnerabilities manifest themselves across multiple parts of a program, Melange performs both local and global analyses. To scale up to large programs, global analysis is demand-driven. Our prototype detects multiple vulnerability classes in C and C++ code including type confusion, and garbage memory reads. We have evaluated Melange extensively. Our case studies show that Melange scales up to large codebases such as Chromium, is easy-to-use, and most importantly, capable of discovering vulnerabilities in real-world code. Our findings indicate that static analysis is a viable reinforcement to the software testing tool set.Comment: A revised version to appear in the proceedings of the 13th conference on Detection of Intrusions and Malware & Vulnerability Assessment (DIMVA), July 201

A document analysis of the visibility of sustainability in TVE teacher education programme: the case of a Malaysian HEI

There has been a global call for institutions of learning to engage in Education for Sustainable Development (ESD) by leading world organisations. Although scholars advocate for an interdisciplinary approach to sustainability, the research literature shows that majority of sustainability issues are addressed through fields such as environmental and developmental education. There has also been a call for the integration of Sustainable Development (SD) in Technical and Vocational Education and Training (TVET) programmes by various scholars and bodies such as the United Nations Education, Scientific and Cultural Organisation (UNESCO). The issue, however, is that Technical and Vocational Education (TVE) programmes are not yet embracing this call to integrate ESD into their programmes. Hence, it is imperative to reiterate the intersection between TVE and SD and how the former can contribute significantly to the SD agenda. Therefore, by completing a qualitative documentary analysis of a TVE programme, using a Malaysian Higher Education Institution (HEI) as a case study, this paper discusses the visibility of sustainability in TVE programmes as well as explores the overarching goal of ESD and why it is especially crucial for TVE. Findings reveal that the concept of sustainability is only barely reflected in the TVE teacher training curriculum. Recommendations for practice change and further research are presented and discussed

A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks

With the complexity of nanoelectronic devices rapidly increasing, an efficient way to handle large number of embedded instruments became a necessity. The IEEE 1687 standard was introduced to provide flexibility in accessing and controlling such instrumentation through a reconfigurable scan chain. Nowadays, together with testing the system for defects that may affect the scan chains themselves, the diagnosis of such faults is also important. This article proposes a method for generating stimuli to precisely identify permanent high-level faults in a IEEE 1687 reconfigurable scan chain: the system is modeled as a finite state automaton where faults correspond to multiple incorrect transitions; then, a dynamic greedy algorithm is used to select a sequence of inputs able to distinguish between all possible faults. Experimental results on the widely-adopted ITC'02 and ITC'16 benchmark suites, as well as on synthetically generated circuits, clearly demonstrate the applicability and effectiveness of the proposed approach: generated sequences are two orders of magnitude shorter compared to previous methodologies, while the computational resources required remain acceptable even for larger benchmarks

New techniques for functional testing of microprocessor based systems

Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product. Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices. Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests. In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent. My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products. Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks