Evaluation of advanced techniques for structural FPGA self-test

This thesis presents a comprehensive test generation framework for FPGA logic elements and interconnects. It is based on and extends the current state-of-the-art. The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is performed on a portion of the FPGA before it is reconfigured as part of the system to ensure that the FPGA fabric is fault-free. The implementation platform is the Xilinx Virtex-5 FPGA family. Existing literature in FPGA testing is evaluated and reviewed thoroughly. The various approaches are compared against one another qualitatively and the approach most suitable to the target platform is chosen. The array testing method is employed in testing the FPGA logic for its low hardware overhead and optimal test time. All tests are additionally pipelined to reduce test application time and use a high test clock frequency. A hybrid fault model including both structural and functional faults is assumed. An algorithm for the optimization of the number of required FPGA test configurations is developed and implemented in Java using a pseudo-random set-covering heuristic. Optimal solutions are obtained for Virtex-5 logic slices. The algorithm effort is parameterizable with the number of loop iterations each of which take approximately one second for a Virtex-5 sliceL circuit. A flexible test architecture for interconnects is developed. Arbitrary wire types can be tested in the same test configuration with no hardware overhead. Furthermore, a routing algorithm is integrated with the test template generation to select the wires under test and route them appropriately. Nine test configurations are required to achieve full test coverage for the FPGA logic. For interconnect testing, a local router-based on depth-first graph traversal is implemented in Java as the basis for creating systematic interconnect test templates. Pent wire testing is additionally implemented as a proof of concept. The test clock frequency for all tests exceeds 170 MHz and the hardware overhead is always lower than seven CLBs. All implemented tests are parameterizable such that they can be applied to any portion of the FPGA regardless of size or position

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Cyber-Physical Systems Enabled By Unmanned Aerial System-Based Personal Remote Sensing: Data Mission Quality-Centric Design Architectures

In the coming 20 years, unmanned aerial data collection will be of great importance to many sectors of civilian life. Of these systems, Personal Remote Sensing (PRS) Small Unmanned Aerial Systems (sUASs), which are designed for scientic data collection, will need special attention due to their low cost and high value for farming, scientic, and search-andrescue uses, among countless others. Cyber-Physical Systems (CPSs: large-scale, pervasive automated systems that tightly couple sensing and actuation through technology and the environment) can use sUASs as sensors and actuators, leading to even greater possibilities for benet from sUASs. However, this nascent robotic technology presents as many problems as possibilities due to the challenges surrounding the abilities of these systems to perform safely and eectively for personal, academic, and business use. For these systems, whose missions are dened by the data they are sent to collect, safe and reliable mission quality is of highest importance. Much like the dawning of civil manned aviation, civilian sUAS ights demand privacy, accountability, and other ethical factors for societal integration, while safety of the civilian National Airspace (NAS) is always of utmost importance. While the growing popularity of this technology will drive a great effort to integrate sUASs into the NAS, the only long-term solution to this integration problem is one of proper architecture. In this research, a set of architectural requirements for this integration is presented: the Architecture for Ethical Aerial Information Sensing or AERIS. AERIS provides a cohesive set of requirements for any architecture or set of architectures designed for safe, ethical, accurate aerial data collection. In addition to an overview and showcase of possibilities for sUAS-enabled CPSs, specific examples of AERIS-compatible sUAS architectures using various aerospace design methods are shown. Technical contributions include specic improvements to sUAS payload architecture and control software, inertial navigation and complementary lters, and online energy and health state estimation for lithium-polymer batteries in sUAS missions. Several existing sUASs are proled for their ability to comply with AERIS, and the possibilities of AERIS data-driven missions overall is addressed