Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

TESTING OF MICROPROCESSORS

With the growing use of the microprocessors the problematics of testing become more and more important for the reliability of the instrumentation. The paper gives a survey of the usual strategies and methods for CPU testing in microprocessor controlled equipment. The effects of the state-of-the-art field service methods on the self-test technology are discussed. Description of a new algorithm based on information compression is given together with some related realization experiences

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

Development of an Embedded RTU FDD using Open-Source Monitoring and Control Platform

Previous research on automated fault detection and diagnostics (FDD) for HVAC systems has shown promising benefits like earlier detection and more accurate isolation of different faults. While most researchers, equipment manufacturers, and policymakers agree that HVAC system FDD is important and has the potential to reduce significant energy waste due to faulty system operation, widespread adoption of these tools has been slow. An automated fault detection and diagnosis system has been developed for packaged (rooftop) air conditioners based on the VOLTTRONTM monitoring and controls framework developed by the Department of Energy. The system implements a virtual-sensor-based FDD methodology capable of isolating common rooftop unit faults such as improper refrigerant charge level, heat exchanger fouling, liquid-line restrictions, and compressor valve leakage. A fault impact evaluation component has also been implemented in order to determine the relative impact that faults have on system performance. This is accomplished using virtual sensor outputs and manufacturers’ performance map reference models for performance indices such as cooling capacity and COP. This system has been implemented using low-cost electronics components and was be tested using a 5-ton RTU in a laboratory environment. In this work, a high-level overview of the automated rooftop unit (RTU) FDD system structure will be presented detailing how individual software agents interact along with a description of the computational and network requirements of the system. Alternative system architectures will also be discussed in comparison to the hybrid system presented. A review of the FDD algorithms is also presented that details the virtual sensors implementations along with the methodology to detect, diagnose, and evaluate different faults.  Finally, the performance of the FDD system will be demonstrated using laboratory test data collected for a 4-ton RTU with micro-channel condenser. The goal of this research is to produce a field ready FDD tool for RTUs that can be used to show the benefits of FDD in real systems. Ultimately, the software implementation (using Python) and hardware designs of all the systems components will be released under an open source license in an effort to reduce the engineering effort required by equipment manufacturers interested in a complete AFDD solution

On the use of embedded debug features for permanent and transient fault resilience in microprocessors

Microprocessor-based systems are employed in an increasing number of applications where dependability is a major constraint. For this reason detecting faults arising during normal operation while introducing the least possible penalties is a main concern. Different forms of redundancy have been employed to ensure error-free behavior, while error detection mechanisms can be employed where some detection latency is tolerated. However, the high complexity and the low observability of microprocessors internal resources make the identification of adequate on-line error detection strategies a very challenging task, which can be tackled at circuit or system level. Concerning system-level strategies, a common limitation is in the mechanism used to monitor program execution and then detect errors as soon as possible, so as to reduce their impact on the application. In this work, an on-line error detection approach based on the reuse of available debugging infrastructures is proposed. The approach can be applied to different system architectures profiting from the debug trace port available in most of current microprocessors to observe possible misbehaviors. Two microprocessors have been used to study the applicability of the solution. LEON3 and ARM7TDMI. Results show that the presented fault detection technique enhances observability and thus error detection abilities in microprocessor-based systems without requiring modifications on the core architecture