DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

A Survey on Compiler Autotuning using Machine Learning

Since the mid-1990s, researchers have been trying to use machine-learning based approaches to solve a number of different compiler optimization problems. These techniques primarily enhance the quality of the obtained results and, more importantly, make it feasible to tackle two main compiler optimization problems: optimization selection (choosing which optimizations to apply) and phase-ordering (choosing the order of applying optimizations). The compiler optimization space continues to grow due to the advancement of applications, increasing number of compiler optimizations, and new target architectures. Generic optimization passes in compilers cannot fully leverage newly introduced optimizations and, therefore, cannot keep up with the pace of increasing options. This survey summarizes and classifies the recent advances in using machine learning for the compiler optimization field, particularly on the two major problems of (1) selecting the best optimizations and (2) the phase-ordering of optimizations. The survey highlights the approaches taken so far, the obtained results, the fine-grain classification among different approaches and finally, the influential papers of the field.Comment: version 5.0 (updated on September 2018)- Preprint Version For our Accepted Journal @ ACM CSUR 2018 (42 pages) - This survey will be updated quarterly here (Send me your new published papers to be added in the subsequent version) History: Received November 2016; Revised August 2017; Revised February 2018; Accepted March 2018

MODEL-BASED CONTROL OF AN RCCI ENGINE

Reactivity controlled compression ignition (RCCI) is a combustion strategy that offers high fuel conversion efficiency and near zero emissions of NOx and soot which can help in improving fuel economy in mobile and stationary internal combustion engine (ICE) applications and at the same time lower engine-out emissions. One of the main challenges associated with RCCI combustion is the difficulty in simultaneously controlling combustion phasing, engine load, and cyclic variability during transient engine operations. This thesis focuses on developing model based controllers for cycle-to-cycle combustion phasing and load control during transient operations. A control oriented model (COM) is developed by using mean value models to predict start of combustion (SOC) and crank angle of 50% mass fraction burn (CA50). The COM is validated using transient data from an experimental RCCI engine. The validation results show that the COM is able to capture the experimental trends in CA50 and indicated mean effective pressure (IMEP). The COM is then used to develop a linear quadratic integral (LQI) controller and model predictive controllers (MPC). Premixed ratio (PR) and start of injection (SOI) are the control variables used to control CA50, while the total fuel quantity (FQ) is the engine variable used to control load. The selection between PR and SOI is done using a sensitivity based algorithm. Experimental validation results for reference tracking using LQI and MPC show that the desired CA50 and IMEP can be attained in a single cycle during step-up and step-down transients and yield an average error of less than 1.6 crank angle degrees (CAD) in the CA50 and less than 35 kPa in the IMEP. This thesis presents the first study in the literature to design and implement LQI and MPC combustion controllers for RCCI engines

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Exploring Processor and Memory Architectures for Multimedia

Multimedia has become one of the cornerstones of our 21st century society and, when combined with mobility, has enabled a tremendous evolution of our society. However, joining these two concepts introduces many technical challenges. These range from having sufficient performance for handling multimedia content to having the battery stamina for acceptable mobile usage. When taking a projection of where we are heading, we see these issues becoming ever more challenging by increased mobility as well as advancements in multimedia content, such as introduction of stereoscopic 3D and augmented reality. The increased performance needs for handling multimedia come not only from an ongoing step-up in resolution going from QVGA (320x240) to Full HD (1920x1080) a 27x increase in less than half a decade. On top of this, there is also codec evolution (MPEG-2 to H.264 AVC) that adds to the computational load increase. To meet these performance challenges there has been processing and memory architecture advances (SIMD, out-of-order superscalarity, multicore processing and heterogeneous multilevel memories) in the mobile domain, in conjunction with ever increasing operating frequencies (200MHz to 2GHz) and on-chip memory sizes (128KB to 2-3MB). At the same time there is an increase in requirements for mobility, placing higher demands on battery-powered systems despite the steady increase in battery capacity (500 to 2000mAh). This leaves negative net result in-terms of battery capacity versus performance advances. In order to make optimal use of these architectural advances and to meet the power limitations in mobile systems, there is a need for taking an overall approach on how to best utilize these systems. The right trade-off between performance and power is crucial. On top of these constraints, the flexibility aspects of the system need to be addressed. All this makes it very important to reach the right architectural balance in the system. The first goal for this thesis is to examine multimedia applications and propose a flexible solution that can meet the architectural requirements in a mobile system. Secondly, propose an automated methodology of optimally mapping multimedia data and instructions to a heterogeneous multilevel memory subsystem. The proposed methodology uses constraint programming for solving a multidimensional optimization problem. Results from this work indicate that using today’s most advanced mobile processor technology together with a multi-level heterogeneous on-chip memory subsystem can meet the performance requirements for handling multimedia. By utilizing the automated optimal memory mapping method presented in this thesis lower total power consumption can be achieved, whilst performance for multimedia applications is improved, by employing enhanced memory management. This is achieved through reduced external accesses and better reuse of memory objects. This automatic method shows high accuracy, up to 90%, for predicting multimedia memory accesses for a given architecture

Modeling and Control of Maximum Pressure Rise Rate in RCCI Engines

Low Temperature Combustion (LTC) is a combustion strategy that burns fuel at lower temperatures and leaner mixtures in order to achieve high efficiency and near zero NOx emissions. Since the combustion happens at lower temperatures it inhibits the formation of NOx and soot emissions. One such strategy is Reactivity Controlled Compression Ignition (RCCI). One characteristic of RCCI combustion and LTC com- bustion in general is short burn durations which leads to high Pressure Rise Rates (PRR). This limits the operation of these engines to lower loads as at high loads, the Maximum Pressure Rise Rate (MPRR) hinders the use of this combustion strategy. This thesis focuses on the development of a model based controller that can control the Crank Angle for 50% mass fraction burn (CA50) and Indicated Mean Effective Pressure (IMEP) of an RCCI engine while limiting the MPRR to a pre determined limit. A Control Oriented Model (COM) is developed to predict the MPRR in an RCCI engine. This COM is then validated against experimental data. A statistical analysis of the experimental data is conducted to understand the accuracy of the COM. The results show that the COM is able to predict the MPRR with reasonable accuracy in steady state and transient conditions. Also, the COM is able to capture the trends during transient operation. This COM is then included in an existing cycle by cycle dynamic RCCI engine model and used to develop a Linear Parameter Varying (LPV) representation of an RCCI engine using Data Driven Modeling (DDM) approach with Support Vector Machines (SVM). This LPV representation is then used along with a Model Predictive Controller (MPC) to control the CA50 and IMEP of the RCCI engine model while limiting the MPRR. The controller was able to track the desired CA50 and IMEP with a mean error of 0.9 CAD and 4.7 KPa respectively while maintaining the MPRR below 5.8 bar/CAD

Exploiting partial reconfiguration through PCIe for a microphone array network emulator

The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration