Access Time Minimization in IEEE 1687 Networks

IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the run-time for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Nowadays many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behaviour, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Postprocessing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploratio

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

The broad need to efficiently access all the instrumentation embedded within a semiconductor device called for a standardization, and the reconfigurable scan networks proposed in IEEE 1687 have been demonstrated effective in handling complex infrastructures. At the same time, different techniques have been proposed to test the new circuitry required; however, most of the automatic approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper models the state of a reconfigurable scan network with a finite state automaton, using the length of the active path as the output alphabet and the configurations as input symbols. Permanent faults are represented as incorrect transitions, and a greedy algorithm is used to generate a functional test sequence able to detect all these multiple state-transition faults. The automaton’s state set and the input alphabet are small subsets of the possible ones, and are carefully chosen. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; the test sequences are more efficient than the ones previously generated by search heuristics

Accessing general IEEE Std. 1687 networks via functional ports

Reconfigurable scan networks (RSNs), like IEEE Std. 1687 networks, offer flexible and scalable access to embedded (on- chip) instruments. These networks are typically accessed from the outside via a dedicated test port, like the test access port (TAP) of IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, the IEEE Std. P1687.1 working group is exploring how existing functional ports can be used. Fundamental challenges are to determine what hardware to include in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We have previously shown hardware and protocol to access a limited type of IEEE Std. 1687 networks, known as flat segment insertion bit (SIB)-based networks. In this paper, we present a solution to handle general IEEE Std. 1687 networks. We have made a number of implementations with various benchmarks on an FPGA to evaluate the data overhead and the area usage

On Energy Efficient Inter-Frequency Small Cell Discovery in Heterogeneous Networks

In this paper, we investigate the optimal inter-frequency small cell discovery (ISCD) periodicity for small cells deployed on carrier frequency other than that of the serving macro cell. We consider that the small cells and user terminals (UTs) positions are modelled according to a homogeneous Poisson Point Process (PPP). We utilize polynomial curve fitting to approximate the percentage of time the typical UT missed small cell offloading opportunity, for a fixed small cell density and fixed UT speed. We then derive analytically, the optimal ISCD periodicity that minimizes the average UT energy consumption (EC). Furthermore, we also derive the optimal ISCD periodicity that maximizes the average energy efficiency (EE), i.e. bit-per-joule capacity. Results show that the EC optimal ISCD periodicity always exceeds the EE optimal ISCD periodicity, with the exception of when the average ergodic rates in both tiers are equal, in which the optimal ISCD periodicity in both cases also becomes equal

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches

Experimental multiphase estimation on a chip

Multiparameter estimation is a general problem that aims at measuring unknown physical quantities, obtaining high precision in the process. In this context, the adoption of quantum resources promises a substantial boost in the achievable performances with respect to the classical case. However, several open problems remain to be addressed in the multiparameter scenario. A crucial requirement is the identification of suitable platforms to develop and experimentally test novel efficient methodologies that can be employed in this general framework. We report the experimental implementation of a reconfigurable integrated multimode interferometer designed for the simultaneous estimation of two optical phases. We verify the high-fidelity operation of the implemented device, and demonstrate quantum-enhanced performances in two-phase estimation with respect to the best classical case, post-selected to the number of detected coincidences. This device can be employed to test general adaptive multiphase protocols due to its high reconfigurability level, and represents a powerful platform to investigate the multiparameter estimation scenario.Comment: 10+7 pages, 7+4 figure

MaxSAT Evaluation 2020 : Solver and Benchmark Descriptions

Non peer reviewe