Test Pattern Generation Algorithm Using Structurally Synthesized BDD

Structurally Synthesized Binary DecisionDiagrams (SSBDDs) have an important characteristicproperty of keeping information about circuit’s structure.Boolean difference of a circuit is used to find test pattern forstuck at fault in combinational circuit but the algebraicmanipulation involved in solving Boolean difference is atedious job. In this paper an efficient algorithm is proposed tocompute Boolean difference and test patterns simply usingsearching the paths of SSBDD. This model reduces algebraicmanipulations and takes less time to compute the test pattern

Efficient design of CMOS TSC checkers

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes

A writable programmable logic array

This thesis contains the analysis, design, and implementation of a writable programmable logic array integrated circuit. The WPLA is able to be reprogrammed any number of times as needed. A content addressable scheme is proposed to conduct READ, WRITE, and SEARCH operations in the WPLA. The WPLA is programmed by writing binary data into storage cells associated with each node in the AND/OR planes of the array; the binary data then form the personalities of the PLA. The layout of the WPLA will be implemented using Mentor Graphic\u27s CHIPGRAPH layout editor with 2 µm NMOS technology and MOSIS design rules. The event-driven logic level simulator QUICKSIM, and a MOS circuit level simulator MSIMON, are used to verify the functional and timing behavior of the WPLA

The Complexity of Test Generation at the Transistor Level

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / SRC RSCH 86-12-10

Scalable diversified antirandom test pattern generation with improved fault coverage for black-box circuit testing

Pseudorandom testing is incapable of utilizing the success rate of preceding test patterns while generating subsequent test patterns. Many redundant test patterns have been generated that increase the test length without any significant increase in the fault coverage. An extension to pseudorandom testing is Antirandom that induces divergent patterns by maximizing the Total Hamming Distance (THD) and Total Cartesian Distance (TCD) of every subsequent test pattern. However, the Antirandom test sequence generation algorithm is prone to unsystematic selection when more than one patterns possess maximum THD and TCD. As a result, diversity among test sequences is compromised, lowering the fault coverage. Therefore, this thesis analyses the effect of Hamming distance in vertical as well as horizontal dimension to enhance diversity among test patterns. First contribution of this thesis is the proposal of a Diverse Antirandom (DAR) test pattern generation algorithm. DAR employs Horizontal Total Hamming Distance (HTHD) along with THD and TCD for diversity enhancement among test patterns as maximum distance test pattern generation. The HTHD and TCD are used as distance metrics that increase computational complexity in divergent test sequence generation. Therefore, the second contribution of this thesis is the proposal of tree traversal search method to maximize diversity among test patterns. The proposed method uses bits mutation of a temporary test pattern following a path leading towards maximization of TCD. Results of fault simulations on benchmark circuits have shown that DAR significantly improves the fault coverage up to 18.3% as compared to Antirandom. Moreover, the computational complexity of Antirandom is reduced from exponential O(2n) to linear O(n). Next, the DARalgorithm is modified to ease hardware implementation for on-chip test generation. Therefore, the third contribution of this thesis is the design of a hardware-oriented DAR (HODA) test pattern generator architecture as an alternative to linear feedback shift register (LFSR) that consists of large number of memory elements. Parallel concatenation of the HODA architecture is designed to reduce the number of memory elements by implementing bit slicing architecture. It has been proven through simulation that the proposed architecture has increased fault coverage up to 66% and a reduction of 46.59% gate count compared to the LFSR. Consequently, this thesis presents uniform and scalable test pattern generator architecture for built-in self-test (BIST) applications and solution to maximum distance test pattern generation for high fault coverage in black-box environment

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers