Classical Fault Analysis of MOS VLSI Circuits

Due to the large cost involved in generating effective input vectors to test MOS circuits, finding ways to reduce this test vector generation cost is of considerable interest. In this paper, empirical results show the fault coverage obtained form MOS transistor-level fault simulation using randomly generated test inputs can be approximated by the fault coverage obtained using the test vectors generated from classical stuck-at-zero and stuck-at-one fault simulation on logic-gate-level circuits. Applying this results, an approach is presented to reduce the cost of test vector generation for MOS circuits

A comprehensive comparison between design for testability techniques for total dose testing of flash-based FPGAs

Radiation sources exist in different kinds of environments where electronic devices often operate. Correct device operation is usually affected negatively by radiation. The radiation resultant effect manifests in several forms depending on the operating environment of the device like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). CMOS circuits and Floating gate MOS circuits suffer from an increase in the delay and the leakage current due to TID effect. This may damage the proper operation of the integrated circuit. Exhaustive testing is needed for devices operating in harsh conditions like space and military applications to ensure correct operations in the worst circumstances. The use of worst case test vectors (WCTVs) for testing is strongly recommended by MIL-STD-883, method 1019, which is the standard describing the procedure for testing electronic devices under radiation. However, the difficulty of generating these test vectors hinders their use in radiation testing. Testing digital circuits in the industry is usually done nowadays using design for testability (DFT) techniques as they are very mature and can be relied on. DFT techniques include, but not limited to, ad-hoc technique, built-in self test (BIST), muxed D scan, clocked scan and enhanced scan. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Despite all these recommendations for DFT, radiation testing has not benefited from this reliable technology yet. Also, with the big variation in the DFT techniques, choosing the right technique is the bottleneck to achieve the best results for TID testing. In this thesis, a comprehensive comparison between different DFT techniques for TID testing of flash-based FPGAs is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan technique, clocked scan technique and enhanced scan technique. The comparison is done using ISCAS-89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty of designs bring-up, added delay by DFT logic and robust testable paths in each technique

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 µm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed

System and component design and test of a 10 hp, 18,000 rpm AC dynamometer utilizing a high frequency AC voltage link, part 1

Hard and soft switching test results conducted with one of the samples of first generation MOS-controlled thyristor (MCTs) and similar test results with several different samples of second generation MCT's are reported. A simple chopper circuit is used to investigate the basic switching characteristics of MCT under hard switching and various types of resonant circuits are used to determine soft switching characteristics of MCT under both zero voltage and zero current switching. Next, operation principles of a pulse density modulated converter (PDMC) for three phase (3F) to 3F two-step power conversion via parallel resonant high frequency (HF) AC link are reviewed. The details for the selection of power switches and other power components required for the construction of the power circuit for the second generation 3F to 3F converter system are discussed. The problems encountered in the first generation system are considered. Design and performance of the first generation 3F to 3F power converter system and field oriented induction moter drive based upon a 3 kVA, 20 kHz parallel resonant HF AC link are described. Low harmonic current at the input and output, unity power factor operation of input, and bidirectional flow capability of the system are shown via both computer and experimental results. The work completed on the construction and testing of the second generation converter and field oriented induction motor drive based upon specifications for a 10 hp squirrel cage dynamometer and a 20 kHz parallel resonant HF AC link is discussed. The induction machine is designed to deliver 10 hp or 7.46 kW when operated as an AC-dynamo with power fed back to the source through the converter. Results presented reveal that the proposed power level requires additional energy storage elements to overcome difficulties with a peak link voltage variation problem that limits reaching to the desired power level. The power level test of the second generation converter after the addition of extra energy storage elements to the HF link are described. The importance of the source voltage level to achieve a better current regulation for the source side PDMC is also briefly discussed. The power levels achieved in the motoring mode of operation show that the proposed power levels achieved in the generating mode of operation can also be easily achieved provided that no mechanical speed limitation were present to drive the induction machine at the proposed power level

Constructing a no-reference H.264/AVC bitstream-based video quality metric using genetic programming-based symbolic regression

In order to ensure optimal quality of experience toward end users during video streaming, automatic video quality assessment becomes an important field-of-interest to video service providers. Objective video quality metrics try to estimate perceived quality with high accuracy and in an automated manner. In traditional approaches, these metrics model the complex properties of the human visual system. More recently, however, it has been shown that machine learning approaches can also yield competitive results. In this paper, we present a novel no-reference bitstream-based objective video quality metric that is constructed by genetic programming-based symbolic regression. A key benefit of this approach is that it calculates reliable white-box models that allow us to determine the importance of the parameters. Additionally, these models can provide human insight into the underlying principles of subjective video quality assessment. Numerical results show that perceived quality can be modeled with high accuracy using only parameters extracted from the received video bitstream

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Operational transconductance amplifier-based nonlinear function syntheses

It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirme

Generating All Two-MOS-Transistor Amplifiers Leads to New Wide-Band LNAs

This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-µm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V