Rethinking Wireless: Building Next-Generation Networks

We face a growing challenge to the design, deployment and management of wireless networks that largely stems from the need to operate in an increasingly spectrum-sparse environment, the need for greater concurrency among devices and the need for greater coordination between heterogeneous wireless protocols. Unfortunately, our current wireless networks lack interoperability, are deployed with fixed functions, and omit easy programmability and extensibility from their key design requirements. In this dissertation, we study the design of next-generation wireless networks and analyze the individual components required to build such an infrastructure. Re-designing a wireless architecture must be undertaken carefully to balance new and coordinated multipoint (CoMP) techniques with the backward compatibility necessary to support the large number of existing devices. These next-generation wireless networks will be predominantly software-defined and will have three components: (a) a wireless component that consists of software-defined radio resource units (RRUs) or access points (APs); (b) a software-defined backhaul control plane that manages the transfer of RF data between the RRUs and the centralized processing resource; and (c) a centralized datacenter/cloud compute resource that processes RF signal data from all attached RRUs. The dissertation addresses the following four key problems in next-generation networks: (1) Making Existing Wireless Devices Spectrum-Agile, (2) Cooperative Compression of the Wireless Backhaul, (3) Spectrum Coordination and (4) Spectrum Coordination.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102341/1/zontar_1.pd

Spatial-temporal reasoning applications of computational intelligence in the game of Go and computer networks

Spatial-temporal reasoning is the ability to reason with spatial images or information about space over time. In this dissertation, computational intelligence techniques are applied to computer Go and computer network applications. Among four experiments, the first three are related to the game of Go, and the last one concerns the routing problem in computer networks. The first experiment represents the first training of a modified cellular simultaneous recurrent network (CSRN) trained with cellular particle swarm optimization (PSO). Another contribution is the development of a comprehensive theoretical study of a 2x2 Go research platform with a certified 5 dan Go expert. The proposed architecture successfully trains a 2x2 game tree. The contribution of the second experiment is the development of a computational intelligence algorithm calledcollective cooperative learning (CCL). CCL learns the group size of Go stones on a Go board with zero knowledge by communicating only with the immediate neighbors. An analysis determines the lower bound of a design parameter that guarantees a solution. The contribution of the third experiment is the proposal of a unified system architecture for a Go robot. A prototype Go robot is implemented for the first time in the literature. The last experiment tackles a disruption-tolerant routing problem for a network suffering from link disruption. This experiment represents the first time that the disruption-tolerant routing problem has been formulated with a Markov Decision Process. In addition, the packet delivery rate has been improved under a range of link disruption levels via a reinforcement learning approach --Abstract, page iv

Software-Driven and Virtualized Architectures for Scalable 5G Networks

In this dissertation, we argue that it is essential to rearchitect 4G cellular core networks–sitting between the Internet and the radio access network–to meet the scalability, performance, and flexibility requirements of 5G networks. Today, there is a growing consensus among operators and research community that software-defined networking (SDN), network function virtualization (NFV), and mobile edge computing (MEC) paradigms will be the key ingredients of the next-generation cellular networks. Motivated by these trends, we design and optimize three core network architectures, SoftMoW, SoftBox, and SkyCore, for different network scales, objectives, and conditions. SoftMoW provides global control over nationwide core networks with the ultimate goal of enabling new routing and mobility optimizations. SoftBox attempts to enhance policy enforcement in statewide core networks to enable low-latency, signaling-efficient, and customized services for mobile devices. Sky- Core is aimed at realizing a compact core network for citywide UAV-based radio networks that are going to serve first responders in the future. Network slicing techniques make it possible to deploy these solutions on the same infrastructure in parallel. To better support mobility and provide verifiable security, these architectures can use an addressing scheme that separates network locations and identities with self-certifying, flat and non-aggregatable address components. To benefit the proposed architectures, we designed a high-speed and memory-efficient router, called Caesar, for this type of addressing schemePHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146130/1/moradi_1.pd

Memory Management for Emerging Memory Technologies

The Memory Wall, or the gap between CPU speed and main memory latency, is ever increasing. The latency of Dynamic Random-Access Memory (DRAM) is now of the order of hundreds of CPU cycles. Additionally, the DRAM main memory is experiencing power, performance and capacity constraints that limit process technology scaling. On the other hand, the workloads running on such systems are themselves changing due to virtualization and cloud computing demanding more performance of the data centers. Not only do these workloads have larger working set sizes, but they are also changing the way memory gets used, resulting in higher sharing and increased bandwidth demands. New Non-Volatile Memory technologies (NVM) are emerging as an answer to the current main memory issues. This thesis looks at memory management issues as the emerging memory technologies get integrated into the memory hierarchy. We consider the problems at various levels in the memory hierarchy, including sharing of CPU LLC, traffic management to future non-volatile memories behind the LLC, and extending main memory through the employment of NVM. The first solution we propose is “Adaptive Replacement and Insertion" (ARI), an adaptive approach to last-level CPU cache management, optimizing the cache miss rate and writeback rate simultaneously. Our specific focus is to reduce writebacks as much as possible while maintaining or improving miss rate relative to conventional LRU replacement policy, with minimal hardware overhead. ARI reduces writebacks on benchmarks from SPEC2006 suite on average by 32.9% while also decreasing misses on average by 4.7%. In a PCM based memory system, this decreases energy consumption by 23% compared to LRU and provides a 49% lifetime improvement beyond what is possible with randomized wear-leveling. Our second proposal is “Variable-Timeslice Thread Scheduling" (VATS), an OS kernel-level approach to CPU cache sharing. With modern, large, last-level caches (LLC), the time to fill the LLC is greater than the OS scheduling window. As a result, when a thread aggressively thrashes the LLC by replacing much of the data in it, another thread may not be able to recover its working set before being rescheduled. We isolate the threads in time by increasing their allotted time quanta, and allowing larger periods of time between interfering threads. Our approach, compared to conventional scheduling, mitigates up to 100% of the performance loss caused by CPU LLC interference. The system throughput is boosted by up to 15%. As an unconventional approach to utilizing emerging memory technologies, we present a Ternary Content-Addressable Memory (TCAM) design with Flash transistors. TCAM is successfully used in network routing but can also be utilized in the OS Virtual Memory applications. Based on our layout and circuit simulation experiments, we conclude that our FTCAM block achieves an area improvement of 7.9× and a power improvement of 1.64× compared to a CMOS approach. In order to lower the cost of Main Memory in systems with huge memory demand, it is becoming practical to extend the DRAM in the system with the less-expensive NVMe Flash, for a much lower system cost. However, given the relatively high Flash devices access latency, naively using them as main memory leads to serious performance degradation. We propose OSVPP, a software-only, OS swap-based page prefetching scheme for managing such hybrid DRAM + NVM systems. We show that it is possible to gain about 50% of the lost performance due to swapping into the NVM and thus enable the utilization of such hybrid systems for memory-hungry applications, lowering the memory cost while keeping the performance comparable to the DRAM-only system

Memory Management for Emerging Memory Technologies

The Memory Wall, or the gap between CPU speed and main memory latency, is ever increasing. The latency of Dynamic Random-Access Memory (DRAM) is now of the order of hundreds of CPU cycles. Additionally, the DRAM main memory is experiencing power, performance and capacity constraints that limit process technology scaling. On the other hand, the workloads running on such systems are themselves changing due to virtualization and cloud computing demanding more performance of the data centers. Not only do these workloads have larger working set sizes, but they are also changing the way memory gets used, resulting in higher sharing and increased bandwidth demands. New Non-Volatile Memory technologies (NVM) are emerging as an answer to the current main memory issues. This thesis looks at memory management issues as the emerging memory technologies get integrated into the memory hierarchy. We consider the problems at various levels in the memory hierarchy, including sharing of CPU LLC, traffic management to future non-volatile memories behind the LLC, and extending main memory through the employment of NVM. The first solution we propose is “Adaptive Replacement and Insertion" (ARI), an adaptive approach to last-level CPU cache management, optimizing the cache miss rate and writeback rate simultaneously. Our specific focus is to reduce writebacks as much as possible while maintaining or improving miss rate relative to conventional LRU replacement policy, with minimal hardware overhead. ARI reduces writebacks on benchmarks from SPEC2006 suite on average by 32.9% while also decreasing misses on average by 4.7%. In a PCM based memory system, this decreases energy consumption by 23% compared to LRU and provides a 49% lifetime improvement beyond what is possible with randomized wear-leveling. Our second proposal is “Variable-Timeslice Thread Scheduling" (VATS), an OS kernel-level approach to CPU cache sharing. With modern, large, last-level caches (LLC), the time to fill the LLC is greater than the OS scheduling window. As a result, when a thread aggressively thrashes the LLC by replacing much of the data in it, another thread may not be able to recover its working set before being rescheduled. We isolate the threads in time by increasing their allotted time quanta, and allowing larger periods of time between interfering threads. Our approach, compared to conventional scheduling, mitigates up to 100% of the performance loss caused by CPU LLC interference. The system throughput is boosted by up to 15%. As an unconventional approach to utilizing emerging memory technologies, we present a Ternary Content-Addressable Memory (TCAM) design with Flash transistors. TCAM is successfully used in network routing but can also be utilized in the OS Virtual Memory applications. Based on our layout and circuit simulation experiments, we conclude that our FTCAM block achieves an area improvement of 7.9× and a power improvement of 1.64× compared to a CMOS approach. In order to lower the cost of Main Memory in systems with huge memory demand, it is becoming practical to extend the DRAM in the system with the less-expensive NVMe Flash, for a much lower system cost. However, given the relatively high Flash devices access latency, naively using them as main memory leads to serious performance degradation. We propose OSVPP, a software-only, OS swap-based page prefetching scheme for managing such hybrid DRAM + NVM systems. We show that it is possible to gain about 50% of the lost performance due to swapping into the NVM and thus enable the utilization of such hybrid systems for memory-hungry applications, lowering the memory cost while keeping the performance comparable to the DRAM-only system

Wavelengths switching and allocation algorithms in multicast technology using m-arity tree networks topology

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University London.In this thesis, the m-arity tree networks have been investigated to derive equations for their nodes, links and required wavelengths. The relationship among all parameters such as leaves nodes, destinations, paths and wavelengths has been found. Three situations have been explored, firstly when just one server and the leaves nodes are destinations, secondly when just one server and all other nodes are destinations, thirdly when all nodes are sources and destinations in the same time. The investigation has included binary, ternary, quaternary and finalized by general equations for all m-arity tree networks. Moreover, a multicast technology is analysed in this thesis to transmit data carried by specific wavelengths to several clients. Wavelengths multicast switching is well examined to propose split-convert-split-convert (S-C-S-C) multicast switch which consists of light splitters and wavelengths converters. It has reduced group delay by 13% and 29% compared with split-convert (S-C) and split-convert-split (S-C-S) multicast switches respectively. The proposed switch has also increased the received signal power by a significant value which reaches 28% and 26.92% compared with S-C-S and S-C respectively. In addition, wavelengths allocation algorithms in multicast technology are proposed in this thesis using tree networks topology. Distributed scheme is adopted by placing wavelength assignment controller in all parents’ nodes. Two distributed algorithms proposed shortest wavelength assignment (SWA) and highest number of destinations with shortest wavelength assignment (HND-SWA) algorithms to increase the received signal power, decrease group delay and reduce dispersion. The performance of the SWA algorithm was almost better or same as HND-SWA related to the power, dispersion and group delay but they are always better than other two algorithms. The required numbers of wavelengths and their utilised converters have been examined and calculated for the researched algorithms. The HND-SWA has recorded the superior performance compared with other algorithms. It has reduced number of utilised wavelengths up to about 19% and minimized number of the used wavelengths converters up to about 29%. Finally, the centralised scheme is discussed and researched and proposed a centralised highest number of destinations (CHND) algorithm with static and dynamic scenarios to reduce network capacity decreasing (Cd) after each wavelengths allocation. The CDHND has reduced (Cd) by about 16.7% compared with the other algorithms

Energy-Efficient Softwarized Networks: A Survey

With the dynamic demands and stringent requirements of various applications, networks need to be high-performance, scalable, and adaptive to changes. Researchers and industries view network softwarization as the best enabler for the evolution of networking to tackle current and prospective challenges. Network softwarization must provide programmability and flexibility to network infrastructures and allow agile management, along with higher control for operators. While satisfying the demands and requirements of network services, energy cannot be overlooked, considering the effects on the sustainability of the environment and business. This paper discusses energy efficiency in modern and future networks with three network softwarization technologies: SDN, NFV, and NS, introduced in an energy-oriented context. With that framework in mind, we review the literature based on network scenarios, control/MANO layers, and energy-efficiency strategies. Following that, we compare the references regarding approach, evaluation method, criterion, and metric attributes to demonstrate the state-of-the-art. Last, we analyze the classified literature, summarize lessons learned, and present ten essential concerns to open discussions about future research opportunities on energy-efficient softwarized networks.Comment: Accepted draft for publication in TNSM with minor updates and editin

On the Issues and Challenges of Fiber-Wireless (Fi-Wi) Networks

The objective of this article is to present various aspects of Fiber-Wireless (Fi-Wi) networks, which is a technology of current interest of the researchers. Fiber-wireless technology, known in short as “Fi-Wi,” is a combination of optical-fiber-based network and wireless network. Fi-Wi has recently come forward as one of the emerging future network technologies yet the term is often mixed up with wireless-fidelity (Wi-Fi) technology. In fact, Wi-Fi network could be included in a Fi-Wi architecture. Due to the unfamiliarity with the term, “Fi-Wi” and similar sounding commonly known “Wi-Fi,” many students, even academics and practitioners sometimes may not be able to differentiate between these. In the recent years, a good number of works on various issues of Fi-Wi have come out, but an overall survey with the latest advancements in the area is yet to be found. Hence, in this work, we analyze various issues and challenges of implementing Fi-Wi networks in practical scenarios to allow researchers to find future directions of research and general readers to understand the issues better