An Optimal Gate Design for the Synthesis of Ternary Logic Circuits

Department of Electrical EngineeringOver the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this thesis, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits We propose a methodology for using ternary values effectively in sequential logic. Proposed ternary D flip-flop is designed to normally operate in four-edges of a ternary clock signal. A quad-edge-triggered ternary D flip-flop (QETDFF) is designed with static gates using CNTFET. From HSPICE simulation results, we have confirmed that power-delay-product (PDP) of QETDFF is reduced by 82.31 % compared to state of the art ternary D flip-flop. We synthesize a ternary serial adder using QETDFF. PDP of the proposed ternary serial adder is reduced by 98.23 % compared to state of the art design.ope

Optimizations of Cisco’s Embedded Logic Analyzer Module

Cisco’s embedded logic analyzer module (ELAM) is a debugging device used for many of Cisco’s application specific integrated chips (ASICs). The ELAM is used to capture data of interest to the user and stored for analysis purposes. The user enters a trigger expression containing data fields of interest in the form of a logical equation. The data fields associated with the trigger expression are stored in a set of Match and Mask (MM) registers. Incoming data packets are matched against these registers, and if the user-specified data pattern is detected, the ELAM triggers and begins a countdown sequence to stop data capture. The current ELAM implementation is restricted in the form of trigger expressions that are allowed and in the allocation of resources. Currently, data fields in the trigger expression can only be logically ANDed together, Match and Mask registers are inefficiently utilized, and a static state machine exists in the ELAM trigger logic. To optimize the usage of the ELAM, a trigger expression is first treated as a Boolean expression so that minimization algorithms can be run. Next, the data stored in the Match and Mask registers is analyzed for redundancies. Finally, a dynamic state machine is programmed with a distinct set of states generated from the trigger expression. This set of states is further minimized. A feasibility study is done to analyze the validity of the results

Logic synthesis and optimisation using Reed-Muller expansions

This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR SumOf-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expressions, namely, Fixed Polarity Reed-Muller (FPRM) expansions and KROnecker (KRO) expansions (a category of mixed polarity RM expansions). Initially, the theory of switching functions is comprehensively reviewed. This includes descriptions of various types of RM expansion and ESOP forms. The structure of Binary Decision Diagrams (BDDs) and Reed-Muller Universal Logic Module (RM-ULM) networks are also examined. Heuristic algorithms for deriving optimal (sub-optimal) FPRM expansions of Boolean functions are described. These algorithms are improved forms of an existing tabular technique [1]. Results are presented which illustrate the performance of these new minimisation methods when evaluated against selected existing techniques. An algorithm which may be employed to generate FPRM expansions from incompletely specified Boolean functions is also described. This technique introduces a means of determining the optimum allocation of the Boolean 'don't care' terms so as to derive equivalent minimal FPRM expansions. The tabular technique [1] is extended to allow the representation of KRO expansions. This new method may be employed to generate KRO expansions from either an initial incompletely specified Boolean function or a KRO expansion of different polarity. Additionally, it may be necessary to derive KRO expressions from Boolean Sum-Of-Products (SOP) forms where the product terms are not minterms. A technique is described which forms KRO expansions from disjoint SOP forms without first expanding the SOP expressions to minterm forms. Reed-Muller Binary Decision Diagrams (RMBDDs) are introduced as a graphical means of representing FPRM expansions. RMBDDs are analogous to the BDDs used to represent Boolean functions. Rules are detailed which allow the efficient representation of the initial FPRM expansions and an algorithm is presented which may be employed to determine an optimum (sub-optimum) variable ordering for the RMBDDs. The implementation of RMBDDs as RM-ULM networks is also examined. This thesis is concluded with a review of the algorithms and techniques developed during this research project. The value of these methods are discussed and suggestions are made as to how improved results could have been obtained. Additionally, areas for future work are proposed

Principles of logic design

This study involves logic design and switching theory, in particular their practical application to the logic design and understanding of digital machines. Digital machines, of course, play an extremely important role in that large class of machines known as digital computers. But they also play an important role in many other kinds of practical devices important in the design of communications systems, digital control systems, counters, registers, digital meters, and so on. The basic content of switching theory is very simple. It embodies that body of machines and machine behavior that can be realized with "switches", things that are either "on" or "off", and nothing, really, could be much simpler than that. Of course the world is really comprised of very many complex structures which are really composed of exceedingly simple lesser structures, so that we really shouldn't be too surprised that even though the elements of switching theory are quite simple, their consequences are not necessarily so. The goals of our study are several, and include at least the following: 1) to develop some understanding and capability in using the techniques, design procedures, and models that have been developed for understanding and designing digital networks; 2) to explore in some modest detail the kinds of questions with which logic designers and practitioners concern themselves; 3) to develop an appreciation for the tremendous variation possible in digital design requirements and specifications, i. e,, for the complexity of the 'finite' digital problem, and hence an understanding of the need for systematic design techniques by which to attack such problems; 4) to gain some practice with the fundamental tools and techniques of logic design I so that the reader can adapt the techniques to the "new" problem presented by his own particular design constraints; and 5) to provide an introduction to the literature so that the discerning student can, in the future, dip into the ever growing literature in the field, and find it to some degree comprehensible, and advantageous to use

A study of arithmetic circuits and the effect of utilising Reed-Muller techniques

Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that Reed-Muller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature.This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic.F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in Reed-Muller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions.The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work

Boolean models for genetic regulatory networks

This dissertation attempts to answer some of the vital questions involved in the genetic regulatory networks: inference, optimization and robustness of the mathe- matical models. Network inference constitutes one of the central goals of genomic signal processing. When inferring rule-based Boolean models of genetic regulations, the same values of predictor genes can correspond to di®erent values of the target gene because of inconsistencies in the data set. To resolve this issue, a consistency-based inference method is developed to model a probabilistic genetic regulatory network, which consists of a family of Boolean networks, each governed by a set of regulatory functions. The existence of alternative function outputs can be interpreted as the result of random switches between the constituent networks. This model focuses on the global behavior of genetic networks and re°ects the biological determinism and stochasticity. When inferring a network from microarray data, it is often the case that the sample size is not su±ciently large to infer the network fully, such that it is neces- sary to perform model selection through an optimization procedure. To this end, the network connectivity and the physical realization of the regulatory rules should be taken into consideration. Two algorithms are developed for the purpose. One algo- rithm ¯nds the minimal realization of the network constrained by the connectivity, and the other algorithm is mathematically proven to provide the minimally connected network constrained by the minimal realization. Genetic regulatory networks are subject to modeling uncertainties and perturba- tions, which brings the issue of robustness. From the perspective of network stability, robustness is desirable; however, from the perspective of intervention to exert in- °uence on network behavior, it is undesirable. A theory is developed to study the impact of function perturbations in Boolean networks: It ¯nds the exact number of a®ected state transitions and attractors, and predicts the new state transitions and robust/fragile attractors given a speci¯c perturbation. Based on the theory, one algorithm is proposed to structurally alter the network to achieve a more favorable steady-state distribution, and the other is designed to identify function perturbations that have caused changes in the network behavior, respectively

Preimages for SHA-1

This research explores the problem of finding a preimage — an input that, when passed through a particular function, will result in a pre-specified output — for the compression function of the SHA-1 cryptographic hash. This problem is much more difficult than the problem of finding a collision for a hash function, and preimage attacks for very few popular hash functions are known. The research begins by introducing the field and giving an overview of the existing work in the area. A thorough analysis of the compression function is made, resulting in alternative formulations for both parts of the function, and both statistical and theoretical tools to determine the difficulty of the SHA-1 preimage problem. Different representations (And- Inverter Graph, Binary Decision Diagram, Conjunctive Normal Form, Constraint Satisfaction form, and Disjunctive Normal Form) and associated tools to manipulate and/or analyse these representations are then applied and explored, and results are collected and interpreted. In conclusion, the SHA-1 preimage problem remains unsolved and insoluble for the foreseeable future. The primary issue is one of efficient representation; despite a promising theoretical difficulty, both the diffusion characteristics and the depth of the tree stand in the way of efficient search. Despite this, the research served to confirm and quantify the difficulty of the problem both theoretically, using Schaefer's Theorem, and practically, in the context of different representations