An Error-Based Approximation Sensing Circuit for Event-Triggered, Low Power Wearable Sensors

Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing and storage. However, almost all state-of-the-art systems are still built upon the classical Nyquist-based periodic signal acquisition. In this work, we design and validate the Polygonal Approximation Sampler (PAS), a novel circuit to implement a general-purpose event-based sampler using a polygonal approximation algorithm as the underlying sampling trigger. The circuit can be dynamically reconfigured to produce a coarse or a detailed reconstruction of the analog input, by adjusting the error threshold of the approximation. The proposed circuit is designed at the Register Transfer Level and processes each input sample received from the ADC in a single clock cycle. The PAS has been tested with three different types of archetypal signals captured by wearable devices (electrocardiogram, accelerometer and respiration data) and compared with a standard periodic ADC. These tests show that single-channel signals, with slow variations and constant segments (like the used single-lead ECG and the respiration signals) take great advantage from the used sampling technique, reducing the amount of data used up to 99% without significant performance degradation. At the same time, multi-channel signals (like the six-dimensional accelerometer signal) can still benefit from the designed circuit, achieving a reduction factor up to 80% with minor performance degradation. These results open the door to new types of wearable sensors with reduced size and higher battery lifetime

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Enhanced PON Infrastructure Enabled by Silicon Photonics

Les systèmes de courte portée et de détection directe sont le dernier/premier kilomètre de la fourniture des services Internet d'aujourd'hui. Deux cas d'application sont abordés dans cette thèse, l'un concerne l'amélioration des performances des services Internet par la Fibre-To-TheHome ou les réseaux optiques passifs (PONs). L'autre est le radio access network (RAN) pour le fronthaul. Notre objectif pour RAN est de superposer les signaux 5G sur une infrastructure PON. Nous démontrons expérimentalement la génération d'un signal de répartition multiplexée de fréquences orthogonales (OFDM) à bande latérale unique en utilisant un modulateur IQ sur puce basé sur les photoniques au silicium à micro-anneau. Il s'agit d'une solution à coût bas permettant aux PONs d'augmenter les débits de données grâce à l'utilisation d'OFDM. Nous avons généré un signal OFDM à large bande avec un ratio de suppression de bande latérale de plus de 18 dB. Afin de confirmer la robustesse de la dispersion chromatique (CD), nous transmettons le signal généré OFDM SSB dans plus de 20 km de fibre de monomode standard. Aucun fading induit par la CD n'a été observé et le taux d'erreur sur les bits était bon. Nous proposons une solution de photoniques au silicium pour un réseau optique passif afin de mitiger l'interférence de battement signal-signal (SSBI) dans la transmission OFDM, et de récupérer une partie des porteuses de la liaison descendante pour une utilisation dans la liaison montante. Le sous-système recrée les interférences à une entrée du détecteur équilibré ; le signal de données corrompu par SSBI est à la deuxième entrée. L'annulation se produit via la soustraction dans la détection équilibrée. Comme notre solution de photoniques au silicium (SiP) ne peut pas filtrer les signaux idéalement, nous examinons un facteur d'échelle introduit dans la détection équilibrée qui peut balancer les effets de filtrage non idéaux. Nous montrons expérimentalement l'annulation de l'interférence donne de bonnes performances même avec une porteuse faible, soit pour un ratio porteuse/signal ultra bas de 0 dB. Bien que notre solution soit sensible aux effets de la température, notre démonstration expérimentale montre que le réglage de la fréquence résonante peut dériver jusqu'à 12 GHz de la valeur ciblée et présenter toujours de bonnes performances. Nous effectuons des simulations extensives du schéma d'annulation SSBI proposé, et suggérons une diverse conception polarisée pour le sous-système SiP. Nous examinons via la simulation la vulnérabilité à la variation de température et introduisons une nouvelle métrique de performance : Q-facteur minimum garanti. Nous nous servons de cette métrique pour évaluer la robustesse d'annulation SSBI contre la dérive de fréquence induite par les changements de température. Nous maximisons l'efficacité spectrale sous différentes conditions du système en balayant les paramètres de conception contrôlables. Finalement, les résultats de la simulation du système fournissent des indications sur la conception du résonateur micro-anneau, ainsi que sur le choix de la bande de garde et du format de modulation pour obtenir la plus grande efficacité spectrale. Finalement, nous nous concentrons sur la superposition des signaux 5G sur une infrastructure PON pour RAN. Nous expérimentalement validons un sous-système photonique au silicium conçu pour les réseaux optiques passifs avec réutilisation de porteuses et compatibilité radiosur-fibre (RoF) analogique 5G. Le sous-système permet la détection simultanée des signaux RoF et du signal PON transmis dans une seule tranche assignée de longueur d'onde. Tout en maintenant une qualité suffisante de détection des signaux RoF et PON, il n'y a que la puissance minimale de la porteuse qui est extraite pour chaque détection, ce qui conserve ainsi la puissance de la porteuse pour la modulation de liaison montante. Nous réalisons une suppression efficace du signal de liaison descendante en laissant une porteuse propre et forte pour la remodulation. Nous démontrons expérimentalement le signal RoF de liaison montante via un modulateur à micro-anneau. Nous avons détecté avec succès un signal à large bande de 8 GHz et cinq signaux RoF de 125 MHz simultanément. Et deux signaux RoF de 125 MHz sont remodulés sur la même porteuse. Le signal RoF de liaison montante généré est de 13 dB de plus que les signaux de liaison descendante, ce qui indique leur robustesse contre la diaphonie des signaux résiduels de la liaison descendante.Short reach, direct detection systems are the last/first mile of today's internet service provision. Two use cases are addressed in this thesis, one is for enhancing performance of Internet services on fiber-to-the-home or passive optical networks (PON). The other is radio access networks (RAN) for fronthaul. Our focus for RAN is to overlay 5G signals on a PON infrastructure. We experimentally demonstrate the generation of a single-sideband orthogonal frequency division multiplexed (OFDM) signal using an on-chip silicon photonics microring-based IQ modulator. This is a low cost solution enabling PONs to increase data rates through the use of OFDM. We generated a wideband OFDM signal with over 18 dB sideband suppression ratio. To confirm chromatic dispersion (CD) robustness, we transmit the generated SSB OFDM signal over 20 km of standard single mode fiber. No CD-induced fading was observed and bit error rate was good. We propose a silicon photonics solution for a passive optical network to mitigate signal-signal beat interference (SSBI) in OFDM transmission, and to recuperate a part of the downlink carrier for use in the uplink. The subsystem recreates the interference at one balanced detector input; the data signal corrupted with SSBI is at the second input. Cancellation occurs via subtraction in the balanced detection. As our silicon photonics (SiP) solution cannot filter the signals ideally, we examine a scaling factor to be introduced to the balanced detection that can trade-off the non-ideal filtering effects. We show experimentally that the interference is cancelled, allowing good performance even with a weak carrier, that is, for ultra low carrier to signal ratio of 0 dB. Although our solution is sensitive to temperature effects, our experimental demonstration shows the tuning of the resonant frequency can drift by as much as 12 GHz from the targeted value and still provide good performance. We perform extensive simulations of the proposed SSBI cancellation scheme, and suggest a polarization diverse design for the SiP subsystem. We examine via simulation the vulnerability to temperature variation and introduce a new performance metric: minimum guaranteed Qfactor. We use this metric to evaluate the SSBI cancellation robustness against the frequency drift induced by temperature changes. We maximize the spectral efficiency under different system conditions by sweeping the controllable design parameters. Finally the system simulation results provide guidance on the microring resonator design, as well as choice of guard band and modulation format to achieve the highest spectral efficiency. Finally, we turn to focus on overlay 5G signals on a PON infrastructure for RAN. We experimentally validate a silicon photonic subsystem designed for passive optical networks with carrier reuse and 5G analog radio-over-fiber (RoF) compatibility. The subsystem enables the simultaneous detection of RoF signals and a PON signal transmitted in a single assigned wavelength slot. While maintaining sufficient quality of RoF and PON signal detection, only the minimum carrier power is leached off for each detection, thus conserving carrier power for uplink modulation. We realize effective downlink signal suppression to leave a clean and strong carrier for remodulation. We demonstrate experimentally the RoF uplink signal via a micro ring modulator. We successfully detected an 8 GHz broadband signal and five 125 MHz RoF signals simultaneously. And two 125 MHz radio over fiber signals are remodulated onto the same carrier. The generated uplink RoF signal is 13 dB over the downlink signals, indicating their robustness against the crosstalk from residual downlink signals

Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified