Surface Potential Modelling of Hot Carrier Degradation in CMOS Technology

abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions. Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime. This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created. Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Degradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0,18 µm CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles have been used (gamma rays, X-rays, protons and neutrons) to irradiate the studied devices. Both total ionizing dose (TID) and displacement damage effects are reported. The most sensitive parameter is still the dark current but some quantum eficiency and MOSFET characteristics changes were also observed at higher dose than those of interest for space applications. In all these degradations, the trench isolations play an important role. The consequences on radiation testing for space applications and radiation-hardening-by-design techniques are also discussed

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Modeling and Simulation of the Programmable Metallization Cells (PMCs) and Diamond-Based Power Devices

abstract: This PhD thesis consists of three main themes. The first part focusses on modeling of Silver (Ag)-Chalcogenide glass based resistive memory devices known as the Programmable Metallization Cell (PMC). The proposed models are examined with the Technology Computer Aided Design (TCAD) simulations. In order to find a relationship between electrochemistry and carrier-trap statistics in chalcogenide glass films, an analytical mapping for electron trapping is derived. Then, a physical-based model is proposed in order to explain the dynamic behavior of the photodoping mechanism in lateral PMCs. At the end, in order to extract the time constant of ChG materials, a method which enables us to determine the carriers’ mobility with and without the UV light exposure is proposed. In order to validate these models, the results of TCAD simulations using Silvaco ATLAS are also presented in the study, which show good agreement. In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized. The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Characterization of self-heating effects and assessment of its impact on reliability in finfet technology

The systematically growing power (heat) dissipation in CMOS transistors with each successive technology node is reaching levels which could impact its reliable operation. The emergence of technologies such as bulk/SOI FinFETs has dramatically confined the heat in the device channel due to its vertical geometry and it is expected to further exacerbate with gate-all-around transistors. This work studies heat generation in the channel of semiconductor devices and measures its dissipation by means of wafer level characterization and predictive thermal simulation. The experimental work is based on several existing device thermometry techniques to which additional layout improvements are made in state of the art bulk FinFET and SOI FinFET 14nm technology nodes. The sensors produce excellent matching results which are confirmed through TCAD thermal simulation, differences between sensor types are quantified and error bars on measurements are established. The lateral heat transport measurements determine that heat from the source is mostly dissipated at a distance of 1µm and 1.5µm in bulk FinFET and SOI FinFET, respectively. Heat additivity is successfully confirmed to prove and highlight the fact that the whole system needs to be considered when performing thermal analysis. Furthermore, an investigation is devoted to study self-heating with different layout densities by varying the number of fins and fingers per active region (RX). Fin thermal resistance is measured at different ambient temperatures to show its variation of up to 70% between -40°C to 175°C. Therefore, the Si fin has a more dominant effect in heat transport and its varying thermal conductivity should be taken into account. The effect of ambient temperature on self-heating measurement is confirmed by supplying heat through thermal chuck and adjacent heater devices themselves. Motivation for this work is the continuous evolution of the transistor geometry and use of exotic materials, which in the recent technology nodes made heat removal more challenging. This poses reliability and performance concerns. Therefore, this work studies the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions. Front-end-of-line (FEOL) reliability mechanisms, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB), are studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. By performing an HCI stress at moderate bias conditions, this dissertation shows that the laborious techniques of heat subtraction are no longer necessary. Self-heating is also studied at more realistic device switching conditions by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions and degradation is not distinguishable

Design, scaling and reliability of devices for high-performance mixed-signal applications

This research investigates and gains new understanding on how silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device design couples with both performance scaling and reliability for mixed-signal applications (high-frequency and analog). In addition, this work provides methods of using this knowledge to enhance the predictive modeling of performance and reliability for these devices. The primary objective of this effort is to develop a predictive device modeling methodology and simulation framework that can be used to design new mixed-signal device technologies, and can then be used to assess the device performance and reliability concurrently. Ultimately, the goal is to highlight the need for device performance and reliability in a circuit environment, and establish best practices for practical modeling of these constraints and any resulting trade-offs. To support this objective, several specific areas were targeted to fill the existing gaps in knowledge. This includes developing a technology computer-aided-design (TCAD) based integrated simulation framework and methodology to study performance scaling and reliability in complementary SiGe HBTs; identifying factors determining the predictive nature of the simulated device figures-of-merit (FoM); studying electrothermal constraints for scaling SiGe HBTs on thick-film silicon-on-insulator (SOI) to understand its impact on the DC and RF safe-operating-area (SOA) for the device; and performing reliability studies of hot-carrier damage and annealing in npn and pnp SiGe HBT devices in an effort to gain insight into the physical mechanisms involved and to develop fundamental understanding to aid TCAD modeling of hot-carrier damage in these devices. All of these individual studies resulting from the main research tasks are harmoniously tied together by a central theme: to develop a fundamental understanding about how the device design factors influence both performance scaling and reliability. Some of the key existing challenges and knowledge gaps are addressed by analyzing and reconciling the experimental data with simulation results.Ph.D

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP