A UAV Based CMOS Ku-Band Metasurface FMCW Radar System for Low-Altitude Snowpack Sensing

This article presents development of a UAV based frequency modulated continuous wave (FMCW) radar system for remotely sensing the water contained within snowpacks. To make the radar system compatible with the payload requirements of small UAV platforms, the radar electronics are implemented with CMOS technology, and the antenna is implemented as an extremely compact and lightweight metasurface (MTS) antenna. This article will discuss how the high absorption losses of snowpacks lead to dynamic range requirements much stricter than FMCW radars used for automotive and other sensing applications, and how these requirements are met through antenna isolation, leakage calibration and exploitation of the range correlation effect. The article discusses in detail the implementation of the radar system, the CMOS microwave and digital circuitry, and the MTS antenna. The developed radar was mounted on a drone and conducted surveys in both Idaho and Alaska during the 2022-2023 winter season. We present several of those field results

실시간 근거리 영상화를 위한 MIMO 역합성 개구 레이더 시스템

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 남상욱.Microwave and millimeter wave (micro/mmW) imaging systems have advantages over other imaging systems in that they have penetration properties over non-metallic structures and non-ionization. However, these systems are commercially applicable in limited areas. Depending on the quality and size of the images, a system can be expensive and images cannot be provided in real-time. To overcome the challenges of the current micro/mmW imaging system, it is critical to suggest a new system concept and prove its potential benefits and hazards by demonstrating the testbed. This dissertation presents Ku1DMIC, a wide-band micro/mmW imaging system using Ku-band and 1D-MIMO array, which can overcome the challenges above. For cost-effective 3D imaging capabilities, Ku1DMIC uses 1D-MIMO array configuration and inverse synthetic aperture radar (ISAR) technique. At the same time, Ku1DMIC supports real-time data acquisition through a system-level design of a seamless interface with frequency modulated continuous wave (FMCW) radar. To show the feasibility of 3D imaging with Ku1DMIC and its real-time capabilities, an accelerated imaging algorithm, 1D-MIMO-ISAR RSA, is proposed and demonstrated. The detailed contributions of the dissertation are as follows. First, this dissertation presents Ku1DMIC – a Ku-band MIMO frequency-modulated continuous-wave (FMCW) radar experimental platform with real-time 2D near-field imaging capabilities. The proposed system uses Ku-band to cover the wider illumination area given the limited number of antennas and uses a fast ramp and wide-band FMCW waveform for rapid radar data acquisition while providing high-resolution images. The key design aspect behind the platform is stability, reconfigurability, and real-time capabilities, which allows investigating the exploration of the system’s strengths and weaknesses. To satisfy the design aspect, a digitally assisted platform is proposed and realized based on an AMD-Xilinx UltraScale+ Radio Frequency System on Chip (RFSoC). The experimental investigation for real-time 2D imaging has proved the ability of video-rate imaging at around 60 frames per second. Second, a waveform digital pre-distortion (DPD) method and calibration method are proposed to enhance the image quality. Even if a clean FMCW waveform is generated with the aid of the optimized waveform generator, the signal will inevitably suffer from distortion, especially in the RF subsystem of the platform. In near-field imaging applications, the waveform DPD is not effective at suppressing distortion in wide-band FMCW radar systems. To solve this issue, the LO-DPD architecture and binary search based DPD algorithm are proposed to make the waveform DPD effective in Ku1DMIC. Furthermore, an image-domain optimization correction method is proposed to compensate for the remaining errors that cannot be eliminated by the waveform DPD. For robustness to various unwanted signals such as noise and clutter signals, two regularized least squares problems are applied and compared: the generalized Tikhonov regularization and the total variation (TV) regularization. Through various 2D imaging experiments, it is confirmed that both methods can enhance the image quality by reducing the sidelobe level. Lastly, the research is conducted to realize real-time 3D imaging by applying the ISAR technique to Ku1DMIC. The realization of real-time 3D imaging using 1D-MIMO array configuration is impactful in that this configuration can significantly reduce the costs of the 3D imaging system and enable imaging of moving objects. To this end, the signal model for the 1D-MIMO-ISAR configuration is presented, and then the 1D-MIMO-ISAR range stacking algorithm (RSA) is proposed to accelerate the imaging reconstruction process. The proposed 1D-MIMO-ISAR RSA can reconstruct images within hundreds of milliseconds while maintaining almost the same image quality as the back-projection algorithm, bringing potential use for real-time 3D imaging. It also describes strategies for setting ROI, considering the real-world situations in which objects enter and exit the field of view, and allocating GPU memory. Extensive simulations and experiments have demonstrated the feasibility and potential benefits of 1D-MIMO-IASR configuration and 1D-MIMO-ISAR RSA.마이크로파 및 밀리미터파(micro/mmW) 영상화 시스템은 비금속 구조 및 비이온화에 비해 침투 특성이 있다는 점에서 다른 이미징 시스템에 비해 장점이 있다. 그러나 이러한 시스템은 제한된 영역에서만 상업적으로 적용되고 있다. 이미지의 품질과 크기에 따라 시스템이 매우 고가일 수 있으며 이미지를 실시간으로 제공할 수 없는 현황이다. 현재의 micro/mmW 이미징 시스템의 문제를 극복하려면 새로운 시스템 개념을 제안하고 테스트베드를 시연하여 잠재적인 이점과 위험을 입증하는 것이 중요하다. 본 논문에서는 Ku-band와 1D-MIMO 어레이를 이용한 광대역 micro/mmW 이미징 시스템인 Ku1DMIC를 제안하여 위와 같은 문제점을 극복할 수 있다. 비용 효율적인 3차원 영상화 기능을 위해 Ku1DMIC는 1D-MIMO 배열 기술과 ISAR(Inverse Synthetic Aperture Radar) 기술을 사용한다. 동시에 Ku1DMIC는 주파수 변조 연속파 (FMCW) 레이더와의 원활한 인터페이스의 시스템 수준 설계를 통해 실시간 데이터 수집을 지원한다. Ku1DMIC를 사용한 3차원 영상화의 구현 및 실시간 기능의 가능성을 보여주기 위해, 2차원 영상화를 위한 1D-MIMO RSA과 3차원 영상화를 위한 1D-MIMO-ISAR RSA가 제안되고 Ku1DMIC에서 구현된다. 따라서, 본 학위 논문의 주요 기여는 Ku-band 1D-MIMO 배열 기반 영상화 시스템 프로토타입을 개발 및 테스트하고, ISAR 기반 3차원 영상화 기능을 검사하고, 실시간 3차원 영상화 가능성을 조사하는 것이다. 이에 대한 세부적인 기여 항목은 다음과 같다. 첫째, 실시간 2D 근거리장 이미징 기능을 갖춘 Ku 대역 MIMO 주파수 변조 연속파(FMCW) 레이더 실험 플랫폼인 Ku1DMIC를 제시한다. 제안하는 시스템은 제한된 수의 안테나에서 더 넓은 조명 영역을 커버하기 위해 Ku 대역을 사용하고 고해상도 이미지를 제공하면서 빠른 레이더 데이터 수집을 위해 고속 램프 및 광대역 FMCW 파형을 사용한다. 플랫폼의 핵심 설계 원칙은 안정성, 재구성 가능성 및 실시간 기능으로 시스템의 강점과 약점을 광범위하게 탐색한다. 설계 원칙을 만족시키기 위해 AMD-Xilinx UltraScale+ RFSoC(Radio Frequency System on Chip)를 기반으로 디지털 지원 플랫폼을 제안하고 구현한다. 실시간 2D 이미징에 대한 실험적 조사는 초당 약 60프레임에서 비디오 속도 이미징의 능력을 입증했다. 둘째, 영상 품질 향상을 위한 파형 디지털 전치왜곡(DPD) 방법과 보정 방법을 제안한다. 최적화된 파형 발생기의 도움으로 깨끗한 FMCW 파형이 생성되더라도 특히 플랫폼의 RF 하위 시스템에서 신호는 필연적으로 왜곡을 겪게된다. 근거리 영상화 응용 분야에서는 파형 DPD는 광대역 FMCW 레이더 시스템의 왜곡을 억제하는 데 효과적이지 않다. 이 문제를 해결하기 위해 Ku1DMIC에서 파형 DPD가 유효하도록 LO-DPD 아키텍처와 이진 탐색 기반 DPD 알고리즘을 제안한다. 또한, 파형 DPD로 제거할 수 없는 나머지 오류를 보상하기 위해 이미지 영역 최적화 보정 방법을 제안한다. 노이즈 및 클러터 신호와 같은 다양한 원치 않는 신호에 대한 견고성을 위해 일반화된 Tikhonov 정규화 및 전체 변동(TV) 정규화라는 두 가지 정규화된 최소 자승 문제를 적용 후 비교한다. 다양한 2차원 영상화 실험을 통해 두 방법 모두 부엽 레벨을 줄여 화질을 향상시킬 수 있음을 확인한다. 마지막으로, ISAR 기법을 2차원 영상 플랫폼에 적용하여 실시간 3차원 영상을 구현하기 위한 연구를 진행한다. 1D-MIMO-ISAR 구성에서 실시간 3D 이미징의 구현은 이러한 구성이 3D 이미징 시스템의 비용을 크게 줄일 수 있다는 점에서 영향력이 있다. 따라서 이 논문에서는 1D-MIMO-ISAR 구성에 대한 이미징 재구성을 가속화하기 위해 1D-MIMO-ISAR 범위 스태킹 알고리즘(RSA)을 제안한다. 제안된 1D-MIMO-ISAR RSA는 널리 알려진 Back-Projection 알고리즘과 거의 동일한 이미지 품질을 유지하면서도 수백 밀리초 이내에 이미지를 재구성함으로써 실시간 영상화에 대한 가능성을 보여준다. 또한 물체가 시야에 들어오고 나가는 실제 상황을 고려하기 위한 ROI 설정, 그리고 메모리 할당에 대한 전략을 설명한다. 광범위한 시뮬레이션과 실험을 통해 1D-MIMO-IASR 구성 및 1D-MIMO-ISAR RSA의 가능성과 잠재적 이점을 확인한다.1 INTRODUCTION 1 1.1 Microwave and millimeter-wave imaging 1 1.2 Imaging with radar system 2 1.3 Challenges and motivation 5 1.4 Outline of the dissertation 8 2 FUNDAMENTAL OF TWO-DIMENSIONAL IMAGING USING A MIMO RADAR 9 2.1 Signal model 9 2.2 Consideration of waveform 12 2.3 Image reconstruction algorithm 16 2.3.1 Back-projection algorithm 16 2.3.2 1D-MIMO range-migration algorithm 20 2.3.3 1D-MIMO range stacking algorithm 27 2.4 Sampling criteria and resolution 31 2.5 Simulation results 36 3 MIMO-FMCW RADAR IMPLEMENTATION WITH 16 TX - 16 RX ONE- DIMENSIONAL ARRAYS 46 3.1 Wide-band FMCW waveform generator architecture 46 3.2 Overall system architecture 48 3.3 Antenna and RF transceiver module 53 3.4 Wide-band FMCW waveform generator 55 3.5 FPGA-based digital hardware design 63 3.6 System integration and software design 71 3.7 Testing and measurement 75 3.7.1 Chirp waveform measurement 75 3.7.2 Range profile measurement 77 3.7.3 2-D imaging test 79 4 METHODS OF IMAGE QUALITY ENHANCEMENT 84 4.1 Signal model 84 4.2 Digital pre-distortion of chirp signal 86 4.2.1 Proposed DPD hardware system 86 4.2.2 Proposed DPD algorithm 88 4.2.3 Measurement results 90 4.3 Robust calibration method for signal distortion 97 4.3.1 Signal model 98 4.3.2 Problem formulation 99 4.3.3 Measurement results 105 5 THREE-DIMENSIONAL IMAGING USING 1-D ARRAY SYSTEM AND ISAR TECHNIQUE 110 5.1 Formulation for 1D-MIMO-ISAR RSA 111 5.2 Algorithm implementation 114 5.3 Simulation results 120 5.4 Experimental results 122 6 CONCLUSIONS AND FUTURE WORK 127 6.1 Conclusions 127 6.2 Future work 129 6.2.1 Effects of antenna polarization in the Ku-band 129 6.2.2 Forward-looking near-field ISAR configuration 130 6.2.3 Estimation of the movement errors in ISAR configuration 131 Abstract (In Korean) 145 Acknowlegement 148박

Fully-photonic digital radio over fibre for future super-broadband access network applications

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel UniversityIn this thesis a Fully-Photonic DRoF (FP-DRoF) system is proposed for deploying of future super-broadband access networks. Digital Radio over Fibre (DRoF) is more independent of the fibre network impairments and the length of fibre than the ARoF link. In order for fully optical deployment of the signal conversion techniques in the FP-DRoF architecture, two key components an Analogue-to-Digital Converter (ADC) and a Digital-to-Analogue Converter (DAC)) for data conversion are designed and their performance are investigated whereas the physical functionality is evaluated. The system simulation results of the proposed pipelined Photonic ADC (PADC) show that the PADC has 10 GHz bandwidth around 60 GHz of sampling rate. Furthermore, by changing the bandwidth of the optical bandpass filter, switching to another band of sampling frequency provides optimised performance condition of the PADC. The PADC has low changes on the Effective Number of Bit (ENOB) response versus analogue RF input from 1 GHz up to 22 GHz for 60 GHz sampling frequency. The proposed 8-Bit pipelined PADC performance in terms of ENOB is evaluated at 60 Gigasample/s which is about 4.1. Recently, different methods have been reported by researchers to implement Photonic DACs (PDACs), but their aim was to convert digital electrical signals to the corresponding analogue signal by assisting the optical techniques. In this thesis, a Binary Weighted PDAC (BW-PDAC) is proposed. In this BW-PDAC, optical digital signals are fully optically converted to an analogue signal. The spurious free dynamic range at the output of the PDAC in a back-to-back deployment of the PADC and the PDAC was 26.6 dBc. For further improvement in the system performance, a 3R (Retiming, Reshaping and Reamplifying) regeneration system is proposed in this thesis. Simulation results show that for an ultrashort RZ pulse with a 5% duty cycle at 65 Gbit/s using the proposed 3R regeneration system on a link reduces rms timing jitter by 90% while the regenerated pulse eye opening height is improved by 65%. Finally, in this thesis the proposed FP-DRoF functionality is evaluated whereas its performance is investigated through a dedicated and shared fibre links. The simulation results show (in the case of low level signal to noise ratio, in comparison with ARoF through a dedicated fibre link) that the FP-DRoF has better BER performance than the ARoF in the order of 10-20. Furthermore, in order to realize a BER about 10-25 for the ARoF, the power penalty is about 4 dBm higher than the FP-DRoF link. The simulation results demonstrate that by considering 0.2 dB/km attenuation of a standard single mode fibre, the dedicated fibre length for the FP-DRoF link can be increased to about 20 km more than the ARoF link. Moreover, for performance assessment of the proposed FP-DRoF in a shared fibre link, the BER of the FP-DRoF link is about 10-10 magnitude less than the ARoF link for -19 dBm launched power into the fibre and the power penalty of the ARoF system is 10 dBm more than the FP-DRoF link. It is significant to increase the fibre link’s length of the FP-DRoF access network using common infrastructure. In addition, the simulation results are demonstrated that the FP-DRoF with non-uniform Wavelength Division Multiplexing (WDM) is more robust against four wave mixing impairment than the conventional WDM technique with uniform wavelength allocation and has better performance in terms of BER. It is clearly verified that the lunched power penalty at CS for DRoF link with uniform WDM techniques is about 2 dB higher than non-uniform WDM technique. Furthermore, uniform WDM method requires more bandwidth than non-uniform scheme which depends on the total number of channels and channels spacing

Bluetooth/WLAN receiver design methodology and IC implementations

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Adaptive optical feedforward linearization of optical transceiver for radio over fiber communication link

With the tremendous growth in numbers of mobile data subscribers and explosive demand for mobile data, the current wireless access network need to be augmented in order to keep up with the data speed promised by the future generation mobile network standards. Radio over fiber technology (RoF) is a cost effective solution because of its ability to support numerous numbers of simple structured base stations by consolidating the signal processing functions at the central station. RoF systems are analog systems where noise figure and spurious free dynamic range (SFDR) are important parameters in an RoF link. The nonlinearity of a laser transmitter is a major limiting factor to the performance of an RoF link, as it generates spurious spectral components, leading to intermodulation distortions (IMD), which limit the achievable SFDR of the analog RF wave transmissions. The device nonlinearity can be mitigated through various linearization schemes. The feedforward linearization technique offers a number of advantages compared to other techniques, as it offers good suppression of distortion products over a large bandwidth and supports high operating frequencies. On the other hand, feedforward linearization is a relatively sensitive scheme, where its performance is highly influenced by changing operating conditions such as laser aging, temperature effect, and input signal variations. Therefore, for practical implementations the feedforward system has to be real-time adaptive. This thesis aims to develop an adaptive optical feedforward linearization system for radio over fiber links. Mathematical analyses and computer simulations are performed to determine the most efficient algorithm for the adaptive controller for laser transmitter feedforward linearization system. Experimental setup and practical measurement are performed for an adaptive feedforward linearized laser transmitter and its performance is optimized. The adaptive optical feedforward linearization system has been modeled and simulated in MATLAB Simulink. The performances of two adaptive algorithms, which are related to the gradient signal method, such as least mean square (LMS) and recursive least square (RLS) have been compared. The LMS algorithm has been selected because of its robustness and simplicity. Finally, the adaptive optical feedforward linearization system has been set up with digital signal processor (DSP) as the control device, and practical measurement has been performed. The system has achieved a suppression of 14 dB in the third order IMD products over a bandwidth of 30 MHz, in a two-tone measurement at 1.7 GHz

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies.

Today’s integrated system on chips (SoCs) usually consist of billions of transistors accounting for both digital and analog blocks. Integrating such massive blocks on a single chip involves several challenges, especially when transferring analog blocks from an older technology to newer ones. Furthermore, the exponential growth for IoT devices necessitates small and low power circuits. Hence, new devices and architectures must be investigated to meet the power and area constraints for wireless sensor networks (WSNs). In such cases, design automation becomes an essential tool to reduce the time to market of the circuits. This dissertation focuses on automating the design process of analog designs in advanced CMOS technology nodes, as well as reciprocal quantum logic (RQL) superconducting circuits. For CMOS analog circuits, our design automation technique employs digital automatic placement and routing tools to synthesize and lay out analog blocks along with digital blocks in a cell-based design approach. This technique was demonstrated in the design of a digital-to-analog converter. In the domain of RQL circuits, the automated design of several functional units of a commercial Processor is presented. These automation techniques enable the design of VLSI-scale circuits in this technology. In addition to the investigation of new technologies, several new baseband signal processor architectures are presented in this dissertation. These architectures are suitable for low-power mm3-scale WSNs and enable high frequency transceivers to operate within the power constraints of standalone IoT nodes.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133177/1/elnaz_1.pd