147 research outputs found
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
Multi-band OFDM UWB receiver with narrowband interference suppression
A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible
ultra wideband (UWB) receiver with narrowband interference (NBI) suppression
capability is presented. The average transmit power of UWB system is limited to
-41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it
must operate even in the presence of unintentional radiation of FCC Class-B compatible
devices. If this unintentional radiation resides in the UWB band, it can jam the
communication. Since removing the interference in digital domain requires higher dynamic
range of analog front-end than removing it in analog domain, a programmable
analog notch filter is used to relax the receiver requirements in the presence of NBI.
The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce
the signal swing at the VGA input. The frequency hopping period of MB-OFDM
puts a lower limit on the settling time of the filter, which is inverse proportional to
notch bandwidth. However, notch bandwidth should be low enough not to attenuate
the adjacent OFDM tones. Since these requirements are contradictory, optimization
is needed to maximize overall performance. Two different NBI suppression schemes
are tested. In the first scheme, the notch filter is operating for all sub-bands. In the
second scheme, the notch filter is turned on during the sub-band affected by NBI.
Simulation results indicate that the UWB system with the first and the second suppression
schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be
applied to other frequency hopping systems
Radio-Communications Architectures
Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems
Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication
The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB)
communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s
wireless communications. Frequency synthesis in these communication systems involves
great challenges such as high frequency and wideband operation in addition to stringent
requirements on frequency hopping time and coexistence with other wireless standards.
This research proposes frequency generation schemes for such radio systems and their
integrated implementations in silicon based technologies. Special emphasis is placed on
efficient frequency planning and other system level considerations for building compact
and practical systems for carrier frequency generation in an integrated UWB radio.
This work proposes a frequency band plan for multiband OFDM based UWB
radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency
synthesizers are designed, implemented and tested making them one of the first
frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are
implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband
(SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much
less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz
packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of
2.25 mm2.
Finally, an architecture for a UWB synthesizer is proposed that is based on a
single multiband quadrature VCO, a programmable integer divider with 50% duty cycle
and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the
tuning range requirement of the multiband VCO and leads to a very digitally intensive
architecture for wideband frequency synthesis suitable for implementation in deep
submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while
consuming 90 mW. This architecture provides an efficient solution in terms of area and
power consumption with very low complexity
Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication
The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB)
communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s
wireless communications. Frequency synthesis in these communication systems involves
great challenges such as high frequency and wideband operation in addition to stringent
requirements on frequency hopping time and coexistence with other wireless standards.
This research proposes frequency generation schemes for such radio systems and their
integrated implementations in silicon based technologies. Special emphasis is placed on
efficient frequency planning and other system level considerations for building compact
and practical systems for carrier frequency generation in an integrated UWB radio.
This work proposes a frequency band plan for multiband OFDM based UWB
radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency
synthesizers are designed, implemented and tested making them one of the first
frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are
implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband
(SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much
less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz
packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of
2.25 mm2.
Finally, an architecture for a UWB synthesizer is proposed that is based on a
single multiband quadrature VCO, a programmable integer divider with 50% duty cycle
and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the
tuning range requirement of the multiband VCO and leads to a very digitally intensive
architecture for wideband frequency synthesis suitable for implementation in deep
submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while
consuming 90 mW. This architecture provides an efficient solution in terms of area and
power consumption with very low complexity
A pll based frequency synthesizer in 0.13 um sige bicmos for mb-ofdm uwb systems
With the growing demand for high-speed and high-quality short-range communication, multi-band orthogonal frequency division multiplexing ultra-wide band (MB-OFDM UWB) systems have recently garnered considerable interest in industry and in academia. To achieve a low-cost solution, highly integrated transceivers with small die area and minimum power consumption are required. The key building block of the transceiver is the frequency synthesizer. A frequency synthesizer comprised of two PLLs and one multiplexer is presented in this thesis. Ring oscillators are adopted for PLL implementation in order to drastically reduce the die area of the frequency synthesizer. The poor spectral purity appearing in the frequency synthesizers involving mixers is greatly improved in this design. Based on the specifications derived from application standards, a design methodology is presented to obtain the parameters of building blocks. As well, the simulation results are provided to verify the performance of proposed design
Analysis and design of low power CMOS ultra wideband receiver
This research concentrates on the design and analysis of low power ultra wideband receivers for Multiband Orthogonal Frequency Division Multiplexing systems. Low power design entails different performance tradeoffs, which are analyzed. Relationship among power consumption, achievable noise figure and linearity performance including distortion products (cross-modulation, inter-modulation and harmonic distortion) are derived. From these relationships, circuit design proceeds with allocation of gain among different sub circuit blocks for power optimum system.
A power optimum RF receiver front-end for MB-OFDM based UWB systems is designed that covers all the MB-OFDM spectrum between 3.1 GHZ to 9.6 GHZ. The receiver consists of a low-noise amplifier, down-converter, channel select filter and programmable gain amplifier and occupies only 1mm 2 in 0.13um CMOS process. Receiver consumes 20 mA from a 1.2 V supply and has the measured gain of 69db, noise figure less than 6 dB and input IIP 3 of -6 dBm
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