2,290 research outputs found
A Library-Based Synthesis Methodology for Reversible Logic
In this paper, a library-based synthesis methodology for reversible circuits
is proposed where a reversible specification is considered as a permutation
comprising a set of cycles. To this end, a pre-synthesis optimization step is
introduced to construct a reversible specification from an irreversible
function. In addition, a cycle-based representation model is presented to be
used as an intermediate format in the proposed synthesis methodology. The
selected intermediate format serves as a focal point for all potential
representation models. In order to synthesize a given function, a library
containing seven building blocks is used where each building block is a cycle
of length less than 6. To synthesize large cycles, we also propose a
decomposition algorithm which produces all possible minimal and inequivalent
factorizations for a given cycle of length greater than 5. All decompositions
contain the maximum number of disjoint cycles. The generated decompositions are
used in conjunction with a novel cycle assignment algorithm which is proposed
based on the graph matching problem to select the best possible cycle pairs.
Then, each pair is synthesized by using the available components of the
library. The decomposition algorithm together with the cycle assignment method
are considered as a binding method which selects a building block from the
library for each cycle. Finally, a post-synthesis optimization step is
introduced to optimize the synthesis results in terms of different costs.Comment: 24 pages, 8 figures, Microelectronics Journal, Elsevie
Polynomial-time T-depth Optimization of Clifford+T circuits via Matroid Partitioning
Most work in quantum circuit optimization has been performed in isolation
from the results of quantum fault-tolerance. Here we present a polynomial-time
algorithm for optimizing quantum circuits that takes the actual implementation
of fault-tolerant logical gates into consideration. Our algorithm
re-synthesizes quantum circuits composed of Clifford group and T gates, the
latter being typically the most costly gate in fault-tolerant models, e.g.,
those based on the Steane or surface codes, with the purpose of minimizing both
T-count and T-depth. A major feature of the algorithm is the ability to
re-synthesize circuits with additional ancillae to reduce T-depth at
effectively no cost. The tested benchmarks show up to 65.7% reduction in
T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7%
reduction in T-depth using ancillae.Comment: Version 2 contains substantial improvements and extensions to the
previous version. We describe a new, more robust algorithm and achieve
significantly improved experimental result
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
promising alternative to CMOS technology due to faster speed, smaller size,
lower power consumption, higher scale integration and higher switching
frequency. Also, power dissipation is the main limitation of all the nano
electronics design techniques including the QCA. Researchers have proposed the
various mechanisms to limit this problem. Among them, reversible computing is
considered as the reliable solution to lower the power dissipation. On the
other hand, adders are fundamental circuits for most digital systems. In this
paper, Innovation is divided to three sections. In the first section, a method
for converting irreversible functions to a reversible one is presented. This
method has advantages such as: converting of irreversible functions to
reversible one directly and as optimal. So, in this method, sub-optimal methods
of using of conventional reversible blocks such as Toffoli and Fredkin are not
used, having of minimum number of garbage outputs and so on. Then, Using the
method, two new symmetric and planar designs of reversible full-adders are
presented. In the second section, a new symmetric, planar and fault tolerant
five-input majority gate is proposed. Based on the designed gate, a reversible
full-adder are presented. Also, for this gate, a fault-tolerant analysis is
proposed. And in the third section, three new 8-bit reversible
full-adder/subtractors are designed based on full-adders/subtractors proposed
in the second section. The results are indicative of the outperformance of the
proposed designs in comparison to the best available ones in terms of area,
complexity, delay, reversible/irreversible layout, and also in logic level in
terms of garbage outputs, control inputs, number of majority and NOT gates
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