Low Power Reversible Parallel Binary Adder/Subtractor

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa

Interpolation Methods for Binary and Multivalued Logical Quantum Gate Synthesis

A method for synthesizing quantum gates is presented based on interpolation methods applied to operators in Hilbert space. Starting from the diagonal forms of specific generating seed operators with non-degenerate eigenvalue spectrum one obtains for arity-one a complete family of logical operators corresponding to all the one-argument logical connectives. Scaling-up to n-arity gates is obtained by using the Kronecker product and unitary transformations. The quantum version of the Fourier transform of Boolean functions is presented and a Reed-Muller decomposition for quantum logical gates is derived. The common control gates can be easily obtained by considering the logical correspondence between the control logic operator and the binary propositional logic operator. A new polynomial and exponential formulation of the Toffoli gate is presented. The method has parallels to quantum gate-T optimization methods using powers of multilinear operator polynomials. The method is then applied naturally to alphabets greater than two for multi-valued logical gates used for quantum Fourier transform, min-max decision circuits and multivalued adders

Realization of Ternary Reversible Circuits Using Improved Gate Library

AbstractTernary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli+ (NT ,TT ,TT +). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (NT ,TT ,TT +) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works

Synthesis of Reversible Circuits from a Subset of Muthukrishnan-Stroud Quantum Realizable Multi-Valued Gates

We present a new type of quantum realizable reversible cascade. Next we present a new algorithm to synthesize arbitrary single-output ternary functions using these reversible cascades. The cascades use “Generalized Multi-Valued Gates” introduced here, which extend the concept of Generalized Ternary Gates introduced previously. While there were 216 GTGs, a total of 12 ternary gates of the new type are sufficient to realize arbitrary ternary functions. (The count can be further reduced to 5 gates, three 2-qubit and two 1-qubit). Such gates are realizable in quantum ion trap devices. For some functions, the algorithm requires fewer gates than results previously published [1, 5, 8, 14]. In addition, the algorithm also does conversion from arbitrary ternary logic to reversible logic at the cost of relatively small garbage. The algorithm is implemented here in ternary logic, but generalization to arbitrary radix is both straightforward and sees a reduction in growth of cost as the radix is increased