Explorations for Efficient Reversible Barrel Shifters and Their Mappings in QCA Nanocomputing

This thesis is based on promising computing paradigm of reversible logic which generates unique outputs out of the inputs and. Reversible logic circuits maintain one-to-one mapping inside of the inputs and the outputs. Compared to the traditional irreversible computation, reversible logic circuit has the advantage that it successfully avoids the information loss during computations. Also, reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and the nanocircuits that are testable in nature. Reversible computing circuits require the ancilla inputs and the garbage outputs. Ancilla input is the constant input in reversible circuits. Garbage output is the output for maintaining the reversibility of the reversible logic but is not any of the primary inputs nor a useful bit. An efficient reversible circuit will have the minimal number of garbage and ancilla bits. Barrel shifter is one of main computing systems having applications in high speed digital signal processing, oating-point arithmetic, FPGA, and Center Processing Unit (CPU). It can operate the function of shifting or rotation for multiple bits in only one clock cycle. The goal of this thesis is to design barrel shifters based on the reversible computing that are optimized in terms of the number of ancilla and garbage bits. In order to achieve this goal, a new Super Conservative Reversible Logic Gate (SCRL gate) has been used. The SCRL gate has 1 control input depending on the value of which it can swap any two n-1 data inputs. We proved that the SCRL gate is superior to the existing conservative reversible Fredkin gate. This thesis develops 5 design methodologies for reversible barrel shifters using SCRL gates that are primarily optimized with the criteria of the number of ancilla and garbage bits. The five proposed methodologies consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter and reversible universal bidirectional shifter. The proposed reversible barrel shifter design is compared with the existing works in literature and have shown improvement ranging from 8.5% to 92% by the number of garbage and ancilla bits. The SCRL gate and design methodologies of reversible barrel shifter are mapped in Quantum Dot Cellular Automata (QCA) computing. It is illustrated that the SCRL-based designs of reversible barrel shifters have less QCA cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate- based designs of reversible barrel shifters

DESIGN OF AN EFFICIENT REVERSIBLE LOGIC BASED BIDIRECTIONAL BARREL SHIFTER

Embedded digital signal processors and general purpose processors will use barrel shifters to manipulate data. This paper will present the design of the barrel shifter that performs logical shift right, arithmetic shift right, rotate right, logical shift left, arithmetic shift left, and rotate left operations. The main objective of the upcoming designs is to increase the performance without proportional increase in power consumption. In this regard reversible logic has become most popular technology in the field of low power computing, optical computing, quantum computing and other computing technologies. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated

DESIGN METHODOLOGY OF BIDIRECTIONAL BARREL SHIFTER BASED ON REVERSIBLE LOGIC

Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated

COMPARATIVE ANALYSIS OF 4-BIT AND 8-BIT REVERSIBLE BARREL SHIFTER DESIGNS USING REVKIT

ABSTRACT In the recent years, reversible logic has emerged as a viable approach in power optimization and also has found its importance in low power CMOS, quantum computing, nanotechnology, and optical computing. The main challenge in reversible circuits is to optimize the quantum cost, time delay and the garbage outputs associated with the reversible circuit. 'RevKit' in recent years has become a popular and powerful tool for design visualization, implementation and analysis in reversible computing. In this work, we have implemented the design of reversible 4-bit and 8-bit barrel shifter circuits in RevKit and results are analyzed in terms of quantum cost, delay, garbage outputs, gate count, line count and transistor cost. Further, the simulation results have been documented and tabulated to facilitate a comparative study with conventional designs. Keywords: reversible circuits, barrel shifters, quantum cost, time delay, garbage output, RevKit. INTRODUCTION In irreversible logic computations [1], each bit of information lost generates kTln2 joules of heat energy, where k is Boltzmann's constant and T is the absolute temperature at which the computation is performed. Thus, the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during the computation. The kTln2 energy dissipation can be avoided [2] if a computation is carried out in a reversible manner Rotating and shifting data in a single cycle are required in several applications like efficient computations and arithmetic operations. Barrel shifters, more suitable for this kind of operations, since, it is capable of shifting or rotating the inputs in a single cycle and find great importance in the digital signal processing computation. In reversible system information is not erased. The number of inputs and outputs are equal in reversible gates, which means that the input stage can always be retained from the output stage. Thus, such an implementation of reversible barrel shifter will be highly efficient when compared to any conventional design in terms of time delay, garbage output or the quantum cost associated with such a structure. The majority of the work that currently exists in literature focuses on optimizing the reversible sequential designs in terms of number of reversible gates and garbage outputs using functional verification. A few prior works have used design tools such as RevKi

Development of aerogel Cherenkov counters at Novosibirsk

Abstract The work on aerogel Cherenkov counters was started in Novosibirsk in 1986. Production of aerogels with refractive indices of 1.006–1.13 and thicknesses of blocks up to 50 mm was developed. The light absorption length at 400 nm is 5–7 m, the scattering length is 4–5 cm. By these parameters, the Novosibirsk aerogel is one of the best in the world. The ASHIPH Cherenkov counters with light collection on wavelength shifters have been developed. The ASHIPH system of the KEDR detector contains 1000 l of aerogel. The π / K separation is 4.5 σ . A project of ASHIPH counters for the SND detector has been developed. Aerogel RICH for LHCb gives a possibility to identify hadrons in the momentum range of 2–10 GeV/c. The Novosibirsk group is developing an aerogel RICH for the endcap for the SuperBaBar project. Calculations performed by a group of physicists from Novosibirsk and DESY-Zeuthen have shown that aerogel radiators enable to achieve time resolution up to 20 fs

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements

MF-RALU: design of an efficient multi-functional reversible arithmetic and logic unit for processor design on field programmable gate array platform

Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a <11% chip area and consumes 332 mW total power. The RISC processor utilizes a <3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA

VLSI design concepts for iterative algorithms

Circuit design becomes more and more complicated, especially when the Very Large Scale Integration (VLSI) manufacturing technology node keeps shrinking down to nanoscale level. New challenges come up such as an increasing gap between the design productivity and the Moore’s Law. Leakage power becomes a major factor of the power consumption and traditional shared bus transmission is the critical bottleneck in the billion transistors Multi-Processor System–on–Chip (MPSoC) designs. These issues lead us to discuss the impact on the design of iterative algorithms. This thesis presents several strategies that satisfy various design con- straints, which can be used to explore superior solutions for the circuit design of iterative algorithms. Four selected examples of iterative al- gorithms are elaborated in this respect: hardware implementation of COordinate Rotation DIgital Computer (CORDIC) processor for sig- nal processing, configurable DCT and integer transformations based CORDIC algorithm for image/video compression, parallel Jacobi Eigen- value Decomposition (EVD) method with arbitrary iterations for com- munication, and acceleration of parallel Sparse Matrix–Vector Multipli- cation (SMVM) operations based Network–on–Chip (NoC) for solving systems of linear equations. These four applications of iterative meth- ods have been chosen since they cover a wide area of current signal processing tasks. Each method has its own unique design criteria when it comes to the direct implementation on the circuit level. Therefore, a balanced solution between various design tradeoffs is elaborated for each method. These tradeoffs are between throughput and power consumption, com- putational complexity and transformation accuracy, the number of in- ner/outer iterations and energy consumption, data structure and net- work topology. It is shown that all of these algorithms can be imple- mented on FPGA devices or as ASICs efficiently