Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design

International audienceModern SoC design may rely on models, or on highlevel description languages. Although very close, the benefits obtained from either sides can be substantially different (and mismatch may occur). The IP-Xact formalism, now a standard (IEEE 1685), was introduced to help assemble component IP from distinct sources into an integrated design. Components could be expressed in high-level HDLs such as SystemC, so should be the full design after translation. Experience shows that in fact this is hardly the case, specially in publicly available methods and tools. The present contribution goes one step into linking SystemC designs to their IP-Xact structural representation by translation. It then exports the resulting IP-Xact model into the UML/MARTE profile modeling framework, to allow to annotating existing models with additional information (again in a publicly available fashion, as opposed to vendor extensions). Even if our approach is still far from being complete, it bridges a number of gaps induce by the combined uses of SystemC and IP-Xact

Normal Forms and Equivalence of K-periodically Routed Graphs

We introduce K-periodically Routed Graphs, which are extensions of Marked Graphs with routing nodes, governed by ultimately periodic binary sequences. We study data relations and dependencies, as well as equational transformations of the network topology. We show the existence of expanded normal forms. We prove that some transformations preserve external flow equivalence. Issues arising from internal flow interleavings and permutations are also tackled

UML/MARTE pour la spécicationd'exigences systèmes (version étendue)

To verify embedded systems early in the design stages, we need formal ways to requirements specification which can be as close as possible to natural language interpretation, away from the lower ESL/RTL levels. This paper proposes to contribute to the FSL (Formal Specification Level) by specifying natural language requirements graphically in the form of temporal patterns. Standard modeling artifacts like UML and MARTE are used to provide formal semantics of these graphical models allowing to eliminate ambiguity in specifications and automatic design verification at different abstraction levels using these patterns.Pour vérifier des systèmes embarqués tôt dans le cycle de conception, il est nécessaire de disposerde langages d'exigences aussi proche que possible de l'expression des besoins en langage naturel. Ce papier s'inscrit dans l'initiative FSL (Formal Specification Level) et propose un langage graphique, s'appuyant sur UML pour décrire des exigences formelles basées sur un ensemble de patrons temporels. Il réutilise très largement des constructions UML et MARTE et s'appuie sur la sémantique du langage CCSL pour éliminer les ambiguïtés dans les spécifications, exécuterles modèles et permettre la vérification de ces modèles au niveau système

A Framework to Specify System Requirements using Natural interpretation of UML/MARTE diagrams

International audienceThe ever-increasing design complexity of embedded systems is constantly pressing the demand for more abstract design levels and possible methods for automatic verification and synthesis. Transforming a text-based user requirements document into semantically sound models is always difficult and error-prone as mostly these requirements are vague and improperly documented. This paper presents a framework to specify textual requirements graphically in standard modeling formalisms like uml and marte in the form of temporal and logical patterns. The underlying formal semantics of these graphical models allow to eliminate ambiguity in specifications and automatic design verification at different abstraction levels using these patterns. The semantics of these operators/patterns are presented formally as state automatons and a comparison is made to the existing ccsl relational operators. To reap the benefits of mde, a software plugin TemLoPAC is presented as part of the framework to transform the graphical patterns into ccsl and Verilog-based observers

Improved False Causal Loop Detection in Polychronous Specificationof Embedded Software

As opposed to single clocked synchronous programming paradigms, polychronous formalism allows specification of concurrent data flow computation on signals such that various data flows can evolve asynchronous with respect to each other. Explicit constraints and constraints implied by the syntactic structures impart certain intrinsic properties to models specified polychronously. One of the major steps in designing a synthesis engine for polychronous specifications is the characterization of specified models into categories such as inherently sequential or inherently multi-threaded. In this paper, we are concerned with sequentially implementable polychronous specification where computation is divided into a totally ordered sequence of logical instants. Data flow computation within an instant happens based on the implied data flow order. This order or data dependency often varies from one instant to another. Thus determining if there is an instant at which the data flow order forms a causal cycle is an important problem. In the current polychronous compilers, such as SIGNAL compiler and EmCodeSyn, this is solved without due effort, by rejecting any program which has a buffer-free structural cycle. However, a clocked dependency graph can be used to construct logical constraints representing the instants with a possible causal loop. The satisfiability of such constraints would imply that such a loop is realizable and hence the specification has a possible deadlock. The reachability of this instant with a given set of initial conditions would verify if the program should be rejected. In the past, the work on such constraints and their satisfiability has not been implemented even though for pure Boolean signals and clocks this could have been done using a satisfiability solver. With the advent to SAT modulo theory (SMT) solvers, this can now be extended to a more general class of specifications. Moreover, model checking on an abstraction of the specification can provide more information about the reachability of instants at which cyclic data dependency is realized. This paper presents an improved polychronous synthesis tool accepting a much larger class of specifications than could be done before. In our experimental results, we demonstrate the capabilities of our causality analysis methods and show that our synthesis tool performs better than previous strategies, including our own past work

Model-based passive testing of safety-critical components

Passive testing is a complementary technique to active testing. For some types of systems, for example dynamic or adaptive distributed systems which are able to re-configure themselves at runtime in response to changes in their environments, exhaustive active testing before deployment is either theoretically impossible or practically not feasible. For such types of systems the additional application of the technique of passive testing is recommendable. However, a comprehensive theory and taxonomy of methods and techniques for model-based passive testing does –as far as we know– not yet exist and is from today’s perspective still very much a topic for future research in this domain. For this reason the presentation of the topic in this chapter is very much example-based such as to provide the reader with some first intuitions about what model-based passive testing is, what kinds of techniques could be used to implement it, and what could be some typical application scenarios for model-based passive testing in the domains of software systems, hardware systems, as well as embedded software+hardware systems.Note: Section 5 of our chapter, as well as several Figures and a number of Acknowledgments, which will appear in the above-mentioned book, are OMITTED in this pre-print version.http://www.crcpress.com/product/isbn/978143981845