An Integral Battery Charger with Power Factor Correction for Electric Scooter

This paper presents an integral battery charger for an electric scooter with high voltage batteries and interior-permanent-magnet motor traction drive. The battery charger is derived from the power hardware of the scooter, with the ac motor drive that operates as three-phase boost rectifier with power factor correction capability. The control of the charger is also integrated into the scooter control firmware that is implemented on a fixed-point DSP controller. Current-controlled or voltage-controlled charge modes are actuated according to the requirements of the battery management system, that is embedded into the battery pack. With respect to previous integrated chargers, the ac current is absorbed at unitary power factor with no harmonic distortion. Moreover, no additional filtering is needed since the pulsewidth modulation ripple is minimized by means of phase interleaving. The feasibility of the integral charger with different ac motors (induction motor, surface-mounted phase modulation motor) is also discussed, by means of a general model purposely developed for three-phase ac machines. The effectiveness of the proposed battery charger is experimentally demonstrated on a prototype electric scooter, equipped with two Li-ion battery packs rated 260 V, 20 A

Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-impedance patterns

Active gate driving provides an opportunity to reduce EMI in power electronic circuits. Whilst it has been demonstrated for MOS-gated silicon power semiconductor devices, reported advanced gate driving in wide-bandgap devices has been limited to a single impedance change during the device switching transitions. For the first time, this paper shows multi-point gate signal profiling at the sub-ns resolution required for GaN devices. A high-speed, programmable active gate driver is implemented with an integrated high-speed memory and output stage to realise arbitrary gate pull-up and pulldown resistance profiles. The nominal resistance range is 120 μΩ to 64 Ω, and the timing resolution of impedance changes is 150 ps. This driver is used in a 1 MHz GaN bridge leg that represents a synchronous buck converter. It is demonstrated that the gate voltage profile can be manipulated aggressively in nanosecond scale. It is observed that by profiling the first 5 ns of the control device's gate voltage transient, a reduction in switch-node voltage oscillations is observed, resulting in an 8–16 dB reduction in spectral power between 400 MHz and 1.8 GHz. This occurs without an increase in switching loss. A small increase in spectral power is seen below 320 MHz. As a baseline for comparison, the GaN bridge leg is operated with a fixed gate drive strength. It is concluded that p-type gate GaN HFETs are actively controllable, and that EMI can be reduced without increasing switching loss

A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit

An On-Chip Sensor for Time Domain Characterization of Electromagnetic Interferences

International audienceWith the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations induced by interference coupling

Techniques for input ripple current cancellation : classification and implementation

Author name used in this publication: J. C. P. LiuAuthor name used in this publication: C. K. TseAuthor name used in this publication: M. H. Pong2000-2001 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishe

A single antenna ambient noise cancellation method for in-situ radiated EMI measurements in the time-domain

This paper presents a single antenna ambient noise cancellation method for in-situ radiated emissions measurements performed using an entirely time-domain approach and the sliding window Empirical Mode Decomposition. The method requires a pair of successive measurements, an initial one for characterizing the ambient noise and a final one for the EMI measurement in the presence of ambient noise. The method assumes the spectral content of the ambient noise is stable between both measurements. The measured time-domain EMI is decomposed into a finite set of intrinsic mode functions. Some modes contain the ambient noise signals while other modes contain the actual components of the EMI. A brute-force search algorithm determines which mode, or combination of modes, maximize the absolute difference between the magnitude of their spectrum and the ambient noise levels for every frequency bin in the measurement bandwidth. Experimental results show the effectiveness of this method for attenuating several ambient noise signals in the 30 MHz – 1 GHz band.Postprint (published version

Common-Mode Noise Cancellation in Switching-Mode Power Supplies Using an Equipotential Transformer Modeling Technique

Electromagnetic interference (EMI) is a significant challenge in the design of high-efficiency switching-mode power supplies due to the presence of common-mode (CM) noise. In many power-supply designs, a variety of noise suppression schemes must be implemented in order to meet EMI requirements. Most of these schemes create power loss that lead to efficiency and thermal issues. In this paper, a transformer construction technique is proposed that effectively reduces the CM noise current injecting across the isolated primary and secondary windings. This technique is based on the zero equipotential line theory. A transformer design with the proposed CM noise cancellation technique can achieve high conversion efficiency as well as substantial CM noise rejection.published_or_final_versio

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER