CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Electronically Tunable Current-mode High-order Ladder Low-pass Filters Based on CMOS Technology

This paper describes the design of current mode low-pass ladder filters based on CMOS technology. The filters are derived from passive RLC ladder filter prototypes using new CMOS lossy and lossless integrators. The all-pole and Elliptic approximations are used in the proposed low-pass filter realizations. The proposed two types of filter can be electronically tuned between 10kHz and 100MHz through bias current from 0.03µA to 300µA. The proposed filters use 1.5 V power supply with 3 mW power consumption at 300 µA bias current. The proposed filters are resistorless, use grounded capacitors and are suitable for further integration. The total harmonic distortion (THD) of the low-pass filters is less than 1% over the operating frequency range. PSPICE simulation results, obtained by using TSMC 0.18µm technology, confirm the presented theory

Palmo : a novel pulsed based signal processing technique for programmable mixed-signal VLSI

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl

Some Application of Switched Current Circuits.

A complete digital signal processing system requires analog circuits acting as an interface between the digital system and the outside analog world. Various techniques have been proposed to implement these circuits, but the one compatible with digital technology is switched capacitor (SC) technique. However, there are still some problems with SC circuits which are as follows: (i) The process technology used for these circuits is not compatible with the standard digital process technology due to extra poly-silicon layer, (ii) the performance of these circuits worsens for low voltage operations, because lower supply voltage will tend to increase power consumption for the same dynamic range, and in order to maintain the same dynamic range on a low supply voltage requires a quadratic increase in sampling capacitance to reduce thermal noise. The required increase in bias current to maintain circuit bandwidth results in a net increase in the overall power consumption. To overcome these problems, a new technique called the switched current (SI) technique has been proposed. The technique utilizes the ability of an MOS transistor to maintain its drain current, when its gate is open circuited, through the charge stored on its gate oxide capacitance. In this technique signals are represented by currents instead of voltages and, therefore, the signal swing is only indirectly limited by a reduction of the available voltage range. In a traditional voltage mode circuit, the supply voltage imposes a direct limitation on signal swing. Switched current circuits could therefore be a better for low voltage operation. 5 The application of switched current systems is much same as for switched capacitor systems viz. filters, A/D and D/A converters, general signal processing etc. but the prime aim is that switched current circuits should be implemented using a standard VLSI. In this work, the SI technique has been studied and several reported SI circuits have been simulated for their performance. Specifically, the work was aimed at the study of developing SI technique for the design of high performance circuits such as Integrators, Differentiators, Programmable filters, A/D and D/A converters, Sigma Delta Modulators, Multipliers, Delays etc. All the investigations are based on the PSPICE simulations using model parameters of the BISIM335 MOS transistors. The investigations match the theoretical interpretations and predictions. The entire gamut of this dissertation has been to study the already reported SI circuits and to investigate them for improved accuracy, dynamic range, bandwidth, linearity and low voltage operation

Digitally-programmable switched-current filters

Digitally-programmable filters have been an ongoing research topic for a number of years. The first such filters were FIR transversal filters using Charge-Coupled Devices (CCD's) and IIR recursive filters using switched-capacitor (SC) techniques. Although both techniques achieve excellent results, they require non-standard and/or additional IC fabrication steps. Low substrate doping is often essential to obtain high charge-transfer efficiency in CCD filters. This is contrary to the trend towards higher doping levels as MOSFETs are scaled. Switched-capacitor circuits require floating linear capacitors that add processing complexity. SC circuits also use voltage operational amplifiers which limit the maximum operating frequency and the minimum power supply voltage. The recently introduced switched-current (SI) technique [1] is an attractive alternative for implementing digitally-programmable filters. SI circuits may be viewed as charge processors where Q= It as opposed to SC circuits wherein Q=CV. Hence, in SI circuits, current rather than voltage is the working variable, and time rather than a capacitance ratio is the precision quantity. No precision circuit elements are required. Therefore, a standard low-voltage scaled digital VLSI CMOS process may be used to implement analog sampled-data SI filters. As current is the working quantity in SI circuits, current signal amplification may be realized using simple current reflection techniques. Because of the low impedance nodes associated with CMOS current mirrors, higher operating frequencies are expected as compared with SC circuits. The low impedance nodes associated with the current amplifiers also suggest reduced power-supply coupling for precision mixed-mode applications. In this study, we present design techniques for digitally programming a second-order SI filter section. While providing similar capabilities to the programmable SC filters [2], the SI circuits have an additional degree of flexibility for optimization in that AC signal currents and/or DC bias currents are programmable. In order to directly compare the SI and SC techniques, the programmable SI filter has been designed to the same specifications as the programmable SC filter of [2]. The programmable second-order section has 63 possible gain (G) values, 63 possible selectivity (Q) values, and 8 possible logarithmically-spaced center frequencies (coo) per octave