Oversampling Successive Approximation Technique for MEMS Differential Capacitive Sensor

This paper proposed an over sampling successive approximation (OSSA) technique to build switched-capacitor capacitance-to-voltage convertor (SC-CVC) for readout circuit of MEMS differential capacitive sensor. The readout circuit employing the OSSA technique has significantly improved resistance to common-mode parasitic capacitance of the input terminal of the readout circuit. In the OSSA readout circuit, there are 5 main non-ideal characteristics: holding error, recovery degradation, increment degradation, rise-edge degradation and charge injection which reduce the accuracy and the settling time of the circuit. These problems are explained in detail and their solutions are given in the paper. The OSSA readout circuit is fabricated in a commercial 0.18um BCD process. To show the improvement evidently, a reported traditional readout circuit is also reproduced and fabricated using the same process. Compared with the traditional readout circuit, the proposed readout circuit reduces the affect of common-mode parasitic capacitance on the accuracy of SC-CVC by more than 23.8 dB, reduces power dissipation by 69.3%, and reduces die area by 50%

Low-voltage data converters

With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve the reliability of gate dielectrics. While the reduction of power supply voltage is of great benefit to the essential digital blocks in the system like data storage and digital signal processing, it makes it hard to operate the important and indispensable analog building blocks such as data converters and drivers. In this thesis, the novel structures for the low-voltage digital-to-analog converter (DAC) and analog-to-digital converter (ADC) are presented. The research contributions of this work include (1) a sub-1V audio [delta sigma] DAC with one opamp used per channel to implement D/A conversion, 1st-order FIR and 2ndorder IIR filtering, as well as power amplification for the headphone, (2) a sub-1V pipelined ADC with the novel MDAC based on a low-voltage track-and-hold amplifier. Two prototypes, one is a 0.8V, 88dB dual-channel audio [delta sigma] DAC with headphone driver, the other one is a 0.8V, 10-bit, 10MS/s pipelined ADC were fabricated to verify the functionality of the proposed structures in standard CMOS processes