A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer (DFE) for applications in wireline communication. A CMOS track-and-regenerate slicer is proposed and employed in the PAM4 receiver. The proposed slicer is designed for the purposes of improving the clock-to-Q delay as well as the output signal swing. A direct DFE in a PAM4 receiver is made possible with the proposed slicer by having rail-to-rail digital feedback signals available with reduced delay, and accordingly relaxing the settling time constraint of the summer. With the 2-tap direct DFE enabled by the proposed slicer, loop-unrolling and inductor-based bandwidth enhancement techniques, which can be area/power intensive, are not necessary at high data rates. The PAM4 receiver fabricated in 28-nm CMOS technology achieves bit-error-rate (BER) better than 1E-12, and energy efficiency of 1.1 pJ/b at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist

Energy-Efficient Receiver Design for High-Speed Interconnects

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers

High speed IC designs for low power short reach optical links

In this thesis, I have briefly introduced the background of my PhD research, current state-of-the-art design, and my PhD research objectives. Then, I demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM’s Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC’s ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM- 4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm 2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only. In the future, system level analysis should be carried out to investigate the critical pattern issue of the PAM4 optical transmitter. The potential solutions toward 1pJ/bit are given (lumped EAM and micro-ring modulator). In addition, the advanced modulation formats (16 QAM, discrete multitone modulation, and FFE) are presented based on the switched capacitor approach

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

대역폭 증대 기술을 이용한 전력 효율적 고속 송신 시스템 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.The high-speed interconnect at the datacenter is being more crucial as 400 Gb Ethernet standards are developed. At the high data rate, channel loss re-quires bandwidth extension techniques for transmitters, even for short-reach channels. On the other hand, as the importance of east-to-west connection is rising, the data center architectures are switching to spine-leaf from traditional ones. In this trend, the number of short-reach optical interconnect is expected to be dominant. The vertical-cavity surface-emitting laser (VCSEL) is a com-monly used optical modulator for short-reach interconnect. However, since VCSEL has low bandwidth and nonlinearity, the optical transmitter also needs bandwidth-increasing techniques. Additionally, the power consumption of data centers reaches a point of concern to affect climate change. Therefore, this the-sis focuses on high-speed, power-efficient transmitters for data center applica-tions. Before the presenting circuit design, bandwidth extension techniques such as fractionally-spaced feed-forward equalizer (FFE), on-chip transmission line, inductive peaking, and T-coil are mathematically analyzed for their effec-tiveness. For the first chip, a power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap FFE based on a slow-wave transmission line is presented. A passive delay line is adopted for generating an equalizer tap to overcome the high clocking power consumption. The transmission line achieves a high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The transmitter includes 4:1 multi-plexers (MUXs) and a quadrature clock generator for high-speed data genera-tion in a quarter-rate system. The 4:1 MUX utilizes a 2-UI pulse generator, and the input configuration is determined by qualitative analysis. The chip is fabri-cated in 65 nm CMOS technology and occupies an area of 0.151 mm2. The proposed transmitter system exhibits an energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling. The second chip presents a power-efficient PAM-4 VCSEL transmitter using 3-tap FFE and negative-k T-coil. The phase interpolators (PIs) generate frac-tionally-spaced FFE tap and correct quadrature phase error. The PAM-4 com-bining 8:1 MUX is proposed rather than combining at output driver with double 4:1 MUXs to reduce serializing power consumption. T-coils at the internal and output node increase the bandwidth and remove inter-symbol interference (ISI). The negative-k T-coil at the output network increases the bandwidth 1.61 times than without T-coil. The VCSEL driver is placed on the high VSS domain for anode driving and power reduction. The chip is fabricated in 40 nm CMOS technology. The proposed VCSEL transmitter operates up to 48 Gb/s NRZ and 64 Gb/s PAM-4 with the power efficiency of 3.03 pJ/b and 2.09 pJ/b, respec-tively.400Gb 이더넷 표준이 개발됨에 따라 데이터 센터의 고속 상호 연결이 더욱 중요해지고 있다. 높은 데이터 속도에서의 채널 손실에 의해 단거리 채널의 경우에도 송신기에 대한 대역폭 확장 기술이 필요하다. 한편, 데이터 센터 내 동-서 연결의 중요성이 높아지면서 데이터 센터 아키텍처가 기존의 아키텍처에서 스파인-리프로 전환되고 있다. 이러한 추세에서 단거리 광학 인터커넥트의 수가 점차 우세해질 것으로 예상된다. 수직 캐비티 표면 방출 레이저(VCSEL)는 일반적으로 단거리 상호 연결을 위해 사용되는 광학 모듈레이터이다. VCSEL은 낮은 대역폭과 비선형성을 가지고 있기 때문에, 광 송신기도 대역폭 증가 기술을 필요로 한다. 또한, 데이터 센터의 전력 소비는 기후 변화에 영향을 미칠 수 있는 우려 지점에 도달했다. 따라서, 본 논문은 데이터 센터 응용을 위한 고속 전력 효율적인 송신기에 초점을 맞추고 있다. 회로 설계를 제시하기 전에, 부분 간격 피드-포워드 이퀄라이저 (FFE), 온칩 전송선로, 인덕터, T-코일과 같은 대역폭 확장 기술을 수학적으로 분석한다. 첫 번째 칩은 저속파 전송선로를 기반으로 한 3-탭 FFE를 사용하는 전력 및 면적 효율적인 펄스-진폭-변조 4(PAM-4) 송신기를 제시한다. 높은 클럭 전력 소비를 극복하기 위해 이퀄라이저 탭 생성을 위해 수동소자 지연 라인을 채택했다. 전송 라인은 차동 동일평면도파관 주위에 이중 플로팅 금속 차폐를 사용하여 15의 높은 전달속도 감쇠를 달성한다. 송신기에는 4:1 멀티플렉서(MUX)와 4-위상 클럭 생성기가 포함되어 있다. 4:1 MUX는 2-UI 펄스 발생기를 사용하며, 정성 분석에 의해 입력 구성이 결정된다. 이 칩은 65 nm CMOS 기술로 제작되었으며 0.151 mm2의 면적을 차지한다. 제안된 송신기 시스템은 PAM-4 신호와 함께 48 Gb/s의 데이터 속도에서 3.03 pJ/b의 에너지 효율을 보여준다. 두 번째 칩에서는 3-탭 FFE 및 역회전 T-코일을 사용하는 전력 효율적인 PAM-4 VCSEL 송신기를 제시한다. 위상 보간기(PI)는 부분 간격 FFE 탭을 생성하고 4-위상 클럭 오류를 수정하는 데 사용된다. 직렬화 전력 소비를 줄이기 위해 출력 드라이버에서 MSB와 LSB를 두 개의 4:1 MUX를 통해 결합하는 대신 8:1 MUX를 통해 PAM-4로 결합하는 회로가 제안된다. 내부 및 출력 노드에서 T-코일은 대역폭을 증가시키고 기호 간 간섭(ISI)을 제거한다. 출력 네트워크에서 역회전 T-코일은 T-코일이 없는 경우보다 대역폭을 1.61배 증가시킨다. VCSEL 드라이버는 양극 구동 및 전력 감소를 위해 높은 VSS 도메인에 배치된다. 이 칩은 40 nm CMOS 기술로 제작되었다. 제안된 VCSEL 송신기는 각각 3.03pJ/b와 2.09pJ/b의 전력 효율로 최대 48Gb/s NRZ와 64Gb/s PAM-4까지 작동한다.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 BACKGROUND OF HIGH-SPEED INTERFACE 6 2.1 OVERVIEW 6 2.2 BASIS OF DATA CENTER ARCHITECTURE 9 2.3 SHORT-REACH INTERFACE STANDARDS 12 2.4 ANALYSES OF BANDWIDTH EXTENSION TECHNIQUES 16 2.4.1 FRACTIONALLY-SPACED FFE 16 2.4.2 TRANSMISSION LINE 21 2.4.3 INDUCTOR 24 2.4.4 T-COIL 33 CHAPTER 3 DESIGN OF 48 GB/S PAM-4 ELECTRICAL TRANSMITTER IN 65 NM CMOS 43 3.1 OVERVIEW 43 3.2 FFE BASED ON DOUBLE-SHIELDED COPLANAR WAVEGUIDE 46 3.2.1 BASIC CONCEPT 46 3.2.2 PROPOSED DOUBLE-SHIELDED COPLANAR WAVEGUIDE 47 3.3 DESIGN CONSIDERATION ON 4:1 MUX 50 3.4 PROPOSED PAM-4 ELECTRICAL TRANSMITTER 53 3.5 MEASUREMENT 57 CHAPTER 4 DESIGN OF 64 GB/S PAM-4 OPTICAL TRANSMITTER IN 40 NM CMOS 64 4.1 OVERVIEW 64 4.2 DESIGN CONSIDERATION OF OPTICAL TRANSMITTER 66 4.3 PROPOSED PAM-4 VCSEL TRANSMITTER 69 4.4 MEASUREMENT 82 CHAPTER 5 CONCLUSIONS 88 BIBLIOGRAPHY 90 초 록 101박