Substrate noise analysis and techniques for mitigation in mixed-signal RF systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 151-158).Mixed-signal circuit design has historically been a challenge for several reasons. Parasitic interactions between analog and digital systems on a single die are one such challenge. Switching transients induced by digital circuits inject noise into the common substrate creating substrate noise. Analog circuits lack the large noise margins of digital circuits, thus making them susceptible to substrate voltage variations. This problem is exacerbated at higher frequencies as the effectiveness of standard isolation technique diminishes considerably. Historically, substrate noise was not a problem because each system was fabricated in its own package shielding it from such interactions. The work in this thesis spans all areas of substrate noise: generation, propagation, and reception. A set of guidelines in designing isolation structures was developed to assist designers in optimizing these structures for a particular application. Furthermore, the effect of substrate noise on two key components of the RF front end, the voltage controlled oscillator (VCO) and the low noise amplifier (LNA), was analyzed. Finally, a CAD tool (SNAT) was developed to efficiently simulate large digital designs to determine substrate noise performance.(cont.) Existing techniques have prohibitively long simulation times and are only suitable for final verification. Determination of substrate noise coupling during the design phase would be extremely beneficial to circuit designers who can incorporate the effect of the noise and re-design accordingly before fabrication. This would reduce the turn around time for circuits and prevent costly redesign. SNAT can be used at any stage of the design cycle to accurately predict (less than 12% error when compared to measurements) the substrate noise performance of any digital circuit with a large degree of computational efficiency.by Nisha Checka.Ph.D

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

Through-substrate interconnects for 3-D integration and RF systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 123-132).Interconnects on silicon chips are fabricated on the top surface with an ever-increasing number of metal layers necessary to just meet performance needs. While devices have scaled according to Moore's law, interconnects have lagged. As metal line widths shrink and line lengths increase, parasitic resistance, capacitance, and inductance degrade circuit performance by increasing delays, loading, and power consumption. Separately, silicon has been supplanting GaAs in low-end, consumer RF applications. Improving the high-frequency performance of silicon by reducing ground inductance will project silicon technology into high-end RF and mm-wave applications. Furthermore, silicon-based systems allow for integration with digital blocks for system-on-chip (SoC). However, this introduces digital noise into the substrate, which interferes with the operation of RF/analog circuits. To address these challenges, we have developed a low-impedance, high-aspect ratio, through-substrate interconnect technology in silicon. Through-substrate vias exploit the third dimension by connecting the front to the backside of a chip so that power, ground, and global signals can be routed on the backside. Substrate vias can also be used to connect chip stacks in system-in-package designs.(cont.) They also provide a low-inductance ground for RFICs and enable a novel way to reduce substrate noise for SoC. The fabrication process features backside patterning for routing of different signals on the back of the chip. Fabricated through-substrate vias were fully characterized using S parameters measured up to 50 GHz. The via resistance, inductance, and sidewall capacitance were extracted from these measurements. We report record-low inductance for high-aspect ratio vias, via resistance less than 1 R, and sidewall capacitance that approaches theory. We have also examined the application of substrate vias arranged as a Faraday cage to reduce substrate noise for SoC. The Faraday cage is exceptional in suppressing substrate crosstalk, especially at high frequencies: 32 dB better than the reference at 10 GHz, and 26 dB at 50 GHz, at a distance of 100 jim. To better understand its performance, we developed a lumped-element, equivalent circuit model. Simulations show that the circuit model accurately represents the noise isolation characteristics of the Faraday cage. Finally, Faraday cage design guidelines for optimum noise isolation are outlined.by Joyce H. Wu.Ph.D

Design of monolithic microwave integrated circuits for 60 GHz band

Potreba za bežicnim komunikacioniom linkovima velikih brzina prenosa podataka je podstaknuta ekspanzijom prenosivih uređaja i multimedijalnih servisa, uz pogodnost da priroda korišcenja dozvoljava a ponekad i zahteva ogranicen domet. Problem kapaciteta komunikacionih linkova i sve veceg broja korisnika se može rešiti prelaskom u opseg ucestanosti od 30 do 300 GHz, koji se naziva i milimetarski opseg. Visoka radna ucestanost pruža mogucnost korišcenja kanala velikog kapaciteta, kao i fizicki malih antenskih nizova za fokusiranje i prostornu lokalizaciju prijemnog i predajnog snopa. Milimetarski opseg nalazi primene i u ostalim oblastima, kao što su industrijske, medicinske i bezbednosne. U komercijalnim primenama od interesa je opseg ucestanosti oko 60 GHz, koji je dodeljen za nelicenciranu upotrebu širom sveta. Razvoj CMOS i BiCMOS tehnologija je omogucio da se sistemi u 60 GHz-om opsegu mogu integrisati u standardnim procesima. Pored viših radnih ucestanosti, skaliranje tehnologija uvodi i tehnološka ogranicenja koja degradiraju performanse ukoliko se njihov uticaj zanemari. Zanemareni efekti mogu doprineti vecim gubicima, koji povecavaju faktor šuma prijemnika i degradiraju efikasnost predajnika, ali i parazitnim preslušavanjima koja rezultuju neželjenim spektralnim komponentama. Stoga je potrebno razmotriti kvalitativne i kvantitativne pokazatelje uticaja tehnoloških ogranicenja na performanse i prilagoditi postupak projektovanja. Kriticni blokovi za domet primopredajnika su malošumni pojacavac na prijemnoj strani i pojacavac snage na predajnoj strani. U okviru teze predstavljen je postupak projektovanja malošumnog pojacavaca i pojacavaca snage za rad u 60 GHz-om opsegu i širokopojasnog delitelja ucestanosti. Uvedene su nove smernice projektovanja koje uzimaju u obzir tehnološka ogranicenja. Pokazano je da se pravilnim particionisanjem elektromagnetskog modela može postici dobro slaganje rezultata simulacije i merenja. Projektovana kola su fabrikovana u IHP Microelectronics korišcenjem 0.25 mm SiGe:C BiCMOS procesa (fT/fmax = 200 GHz). Parametri fabrikovanih kola su izmereni i verifikovani na stopicama cipa, upotrebom mikrotalasnih sondi...The need for high capacity wireless data links is driven by expansion of mobile devices and multimedia services, with the advantage that a typical use case allows, and sometimes demands, a limited range. Problems of limited communication link capacity and growing number of users can be solved by moving to frequency range of 30 - 300 GHz, also known as millimeter range. High operating frequency allows the use of high capacity channels, and physically small antenna arrays for beam steering and spatial localization. Millimeter region of spectrum is also suitable for industrial, scientific and security applications. Unlicensed 60 GHz band is available worldwide, and is attractive for commercial applications. Development of CMOS and BiCMOS technologies has enabled the integration of complete 60 GHz systems in standard processes. Technology scaling enables the use of higher operating frequencies, but imposes new design constraints which may degrade the performance if their effect is neglected. Neglected effects may contribute to higher losses, which increase the noise figure of receiver and degrade transmitter efficiency, and also to parasitic coupling which results in undesired spectral components. Therefore, qualitative and quantitative measure of technology constraints impact on performance degradation needs to be evaluated, and applied to circuit design process. Critical blocks for transceiver range are low noise amplifier on receiver, and power amplifier on transmitter side. Design procedures for 60 GHz low noise and power amplifiers, and wideband frequency divider are presented in this thesis. Guidelines for technology constraints aware design are used in the presented design flow. Good agreement of experimental and simulation results is achieved by proper electromagnetic model partitioning. Designed circuits have been fabricated in IHP Microelectronics 0.25 mm SiGe:C BiCMOS process (fT/fmax = 200 GHz). Test chip parameters have been measured and verified on-wafer by using microwave probes..

Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts

The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models.L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques