An optofluidic router in a low-cost (PDMS) platform for rapid parallel sample analysis

En col·laboració amb la Universitat de Barcelona (UB), la Universitat Autònoma de Barcelona (UAB) i l'Institut de Ciències Fotòniques (ICFO)Optofluidic system for (bio)chemical applications are becoming more demanding in terms of num- ber of control points, number of light sources and readout equipment. So far, most of these sys- tems require several light sources/detectors for suitable performance, increasing their complexity and cost. In this work, we present an easily integrated, fluidically controlled optical router that fa- cilitates coupling of several light sources or detectors. By using PDMS mirrors and phaseguides, the switching liquid is guided and pinned in desired angles, so that the incident light undergoes total internal reflection and can be reflected towards the output channels without any movable parts. The developed router presents ideal performance for lab on a chip applications, achieving switching frequencies between 0.07 ± 0.025 and 4 ± 2 Hz, depending on the flow rate of the switching liquid. The cross-talk levels are at 20 dB from channel output power to static noise level. With the use of parabolic mirrors, channel coupling efficiencies decrease just 2.38 dBm over four channels. The dynamic switching noise reduces the cross-talk levels by 2-5 dB, depending on the incorporation of ink-apertures. The insertion loss of these devices ranges from 17.34 to 25.42 dB. These results prove the viability of the fluidically controlled router in the low-cost PDMS platform. The intended goal of this work has been to simplify and speed up parallel sample analysis with the router integrated into a multiple path photonic component on a single chip. Development on this front is ongoing to rapidly measure methadone concentrations on chip

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with 10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.Comment: 13 pages, 5 figure, journal publicatio

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Laser Assisted Mechanical Micromachining of Hard-to-Machine Materials

There is growing demand for micro and meso scale devices with applications in the field of optics, semiconductor and bio-medical fields. In response to this demand, mechanical micro-cutting (e.g. micro-milling) is emerging as a viable alternative to lithography based micromachining techniques. Mechanical micromachining methods are capable of generating three-dimensional free-form surfaces to sub-micron level precision and micron level accuracies in a wide range of materials including common engineering alloys. However, certain factors limit the types of workpiece materials that can be processed using mechanical micromachining methods. For difficult-to-machine materials such as tool and die steels, limited machine-tool system stiffness and low tool flexural strength are major impediments to the use of mechanical micromachining methods. This thesis presents the design, fabrication and analysis of a novel Laser-assisted Mechanical Micromachining (LAMM) process that has the potential to overcome these limitations. The basic concept involves creating localized thermal softening of the hard material by focusing a solid-state continuous wave laser beam of diameter ranging from 70-120 microns directly in front of a miniature (300 microns-1 mm wide) cutting tool. By suitably controlling the laser power, spot size and speed, it is possible to produce a sufficiently large decrease in flow stress of the work material and, consequently, the cutting forces. This in turn will reduce machine/tool deflection and chances of catastrophic tool failure. The reduced machine/tool deflection yields improved accuracy in the machined feature. In order to use this process effectively, adequate thermal softening needs to be produced while keeping the heat affected zone in the machined surface to a minimum. This has been accomplished in the thesis via a detailed process characterization, modeling of process mechanics and optimization of process variables.Ph.D.Committee Chair: Melkote, Shreyes; Committee Member: Vengazhiyil, Roshan; Committee Member: Graham, Samuel; Committee Member: Johnson, Steven; Committee Member: Liang, Steve