On some properties of the semigroup of a machine which are preserved under state minimization

Some results on special types of semigroups of transformations of a set (including permutation groups) are developed and combined with the fundamental results of Paull and Unger on state minimization of incompletely specified sequential machines to obtain some properties of the transformation semigroup of such a machine which are preserved in all minimum state machines (strong preservation), or in at least one (weak preservation) minimum state machine. The principal results are that for permutation machines (those whose states are permuted by every input) there is strong preservation and for simple machines (those whose semigroups have no proper ideals) there is weak preservation. A number of further properties of permutation machines in the satisfaction and minimum state relations are developed

Synthesis heuristics for large asynchronous sequential circuits

Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii

Asynchronous Logic Design with Flip-Flop Constraints

Some techniques are presented to permit the implementation of asynchronous sequential circuits using standard flip-flops. An algorithm is presented for the RS flip-flop, and it is shown that any flow table may be realized using the algorithm (the flow table is assumed to be realizable using standard logic gates). The approach is shown to be directly applicable to synchronous circuits, and transition flip-flops (JK, D, and T) are analyzed using the ideas developed. Constraints are derived for the flow tables to meet to be realizable using transition flip-flops in asynchronous situations, and upper and lower bounds on the number of transition flip-flops required to implement a given flow table are stated

A new approach to state minimization of finite state machines

A complete program to ease the task of large scale Finite State Machine (FSM) minimization presented in this thesis: TDFM (Two Dimensional FSM Minimizer), is a part of the DIADES system. DIADES is an Automatic Design Synthesis System whose development in the Department of Electrical Engineering at Portland State University is supported in part by a research grant from SHARP Microelectronics Technology

Finite automata and composite realisations.

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State Minimization of Incompletely Specified Sequential Machines

A simple procedure for the state minimization of an incompletely specified sequential machine whose number of internal states is not very large is presented. It introduces the concept of a compatibility graph from which the set of maximal compatibles of the machine can be very conveniently derived. Primary and secondary implication trees associated with each maximal compatible are then constructed. The minimal state machine covering the incompletely specified machine is then obtained from these implication trees