Stability of sinusoidal responses of marginally stable bandpass sigma delta modulators

In this paper, we analyze the stability of the sinusoidal responses of second order interpolative marginally stable bandpass sigma delta modulators (SDMs) with the sum of the numerator and denominator polynomials equal to one and explore new results on the more general second order interpolative marginally stable bandpass SDMs. These results can be further extended to the high order interpolative marginally stable bandpass SDMs

Global stability, limit cycles and chaotic behaviors of second order interpolative sigma delta modulators

It is well known that second order lowpass interpolative sigma delta modulators (SDMs) may suffer from instability and limit cycle problems when the magnitudes of the input signals are at large and at intermediate levels, respectively. In order to solve these problems, we propose to replace the second order lowpass interpolative SDMs to a specific class of second order bandpass interpolative SDMs with the natural frequencies of the loop filters very close to zero. The global stability property of this class of second order bandpass interpolative SDMs is characterized and some interesting phenomena are discussed. Besides, conditions for the occurrence of limit cycle and fractal behaviors are also derived, so that these unwanted behaviors will not happen or can be avoided. Moreover, it is found that these bandpass SDMs may exhibit irregular and conical-like chaotic patterns on the phase plane. By utilizing these chaotic behaviors, these bandpass SDMs can achieve higher signal-to-noise ratio (SNR) and tonal suppression than those of the original lowpass SDMs

Estimation of an initial condition of sigma-delta modulators via projection onto convex sets

Abstract—In this paper, an initial condition of strictly causal rational interpolative sigma-delta modulators (SDMs) is estimated based on quantizer output bit streams and an input signal. A set of initial conditions generating bounded trajectories is characterized. It is found that a set of initial conditions generating bounded trajectories but not necessarily corresponding to quantizer output bit streams is convex. Also, it is found that a set of initial conditions corresponding to quantizer output bit streams but not necessarily generating bounded trajectories is convex too. Moreover, it is found that an initial condition both corresponding to quantizer output bit streams and generating bounded trajectories is uniquely defined if the loop filter is unstable (Here, an unstable loop filter refers to that with at least one of its poles being strictly outside the unit circle). To estimate that unique initial condition, a projection onto convex set approach is employed. Numerical computer simulations show that the employed method can estimate the initial condition effectively

Analysis of Nonlinear Behaviors, Design and Control of Sigma Delta Modulators

M PhilSigma delta modulators (SDMs) have been widely applied in analogue-to-digital (A/D) conversion for many years. SDMs are becoming more and more popular in power electronic circuits because it can be viewed and applied as oversampled A/D converters with low resolution quantizers. The basic structure of an SDM under analytical investigation consists of a loop filter and a low bit quantizer connected by a negative feedback loop. Although there are numerous advantages of SDMs over other A/D converters, the application of SDMs is limited by the unboundedness of the system states and their nonlinear behaviors. It was found that complex dynamical behaviors exist in low bit SDMs, and for a bandpass SDM, the state space dynamics can be represented by elliptic fractal patterns confined within two trapezoidal regions. In all, there are three types of nonlinear behaviors, namely fixed point, limit cycle and chaotic behaviors. Related to the unboundedness issue, divergent behavior of system states is also a commonly discovered phenomenon. Consequently, how to design and control the SDM so that the system states are bounded and the unwanted nonlinear behaviors are avoided is a hot research topic worthy of investigated. In our investigation, we perform analysis on such complex behaviors and determine a control strategy to maintain the boundedness of the system states and avoid the occurrence of limit cycle behavior. For the design problem, we impose constraints based on the performance of an SDM and determine an optimal design for the SDM. The results are significantly better than the existing approaches

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Bandpass delta-sigma modulators for radio receivers

This thesis concerns discrete-time (DT) bandpass (BP) ΔΣ modulators targeted for intermediate frequency (IF) analog-to-digital (A/D) conversion in radio receivers. The receiver architecture adopted has to be capable of operating with different radio frequencies, channel bandwidths, and modulation techniques. This is necessary in order to achieve an extensive operating area and the possibility of utilizing a local mobile phone standard or a standard suitable for a specific service. The digital IF receiver is a good choice for a multi-mode and multi-band mobile phone receiver, because the signal demodulation and channel filtering are performed in the digital domain. This increases the flexibility of the receiver and relieves the design of the baseband part, but an A/D conversion with high dynamic range and low power dissipation is required. BP ΔΣ modulators are capable of converting a high-frequency narrow band signal and are therefore suitable for signal digitization in an IF receiver. First, the theory of BP ΔΣ modulators is introduced. It has been determined that resonators are the most critical circuit blocks in the implementation of a high performance BP ΔΣ modulator. Different DT resonator topologies are studied and a double-delay (DD) resonator is found to be the best candidate for a high quality resonator. A new DD switched-capacitor (SC) resonator structure has been designed. Furthermore, two evolution versions of the designed SC resonator are presented and their nonidealities are analyzed. The three designed DD SC resonator structures are a main point of the thesis, together with the experimental results. Five different DT BP ΔΣ modulator circuit structures have been implemented and measured. All three of the designed SC resonators are used in the implemented circuits. The experimental work consists of both single-bit and multi-bit structures, as well as both single-loop and cascade architectures. The circuits have been implemented with a 0.35 μm (Bi)CMOS technology and operate with a 3.0 V supply. The measured maximum signal-to-noise-and-distortion ratios (SNDRs) are 78 dB over 270 kHz (GSM), 75 dB over 1.25 MHz (IS-95), 69 dB over 1.762 MHz (DECT), and 48 dB over 3.84 MHz (WCDMA) bandwidths using a 60 MHz IF signal.reviewe

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.

Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15

DSP Modulated Class D Audio Amplifier

The goal of this project was to create an 80W, 95% efficient Class D audio amplifier with less than 0.5% harmonic distortion and greater than 100 dB zero-input signal to noise ratio that accepts digital inputs. The amplifier that was built comprised of a three-state digital modulator, an H-bridge amplifier, and a passive filter and was capable of accepting both digital and analog audio inputs by means of the SPDIF protocol and an ADC. To allow the modulator design to be quickly altered, it was implemented on a DSP. Because the modulator could be easily changed, several different modulation schemes were simulated, designed and tested in order to achieve optimal audio quality and efficiency results