Design techniques for dense embedded memory in advanced CMOS technologies

University of Minnesota Ph.D. dissertation. February 2012. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); viii, 116 pages.On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser memories only going to increase as the number of cores in a microprocessor goes up with technology scaling. A commensurate increase in the amount of cache memory is needed to fully utilize the larger and more powerful processing units. 6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. However, the relatively large cell size and conflicting requirements for read and write make aggressive scaling of 6T SRAMs challenging in sub-22 nm. In this dissertation, circuit techniques and simulation methodologies are presented to demonstrate the potential of alternative options such as gain cell eDRAMs and spin-torque-transfer magnetic RAMs (STT-MRAMs) for high density embedded memories.Three unique test chip designs are presented to enhance the retention time and access speed of gain cell eDRAMs. Proposed bit-cells utilize preferential boostings, beneficial couplings, and aggregated cell leakages for expanding signal window between data `1' and `0'. The design space of power-delay product can be further enhanced with various assist schemes that harness the innate properties of gain cell eDRAMs. Experimental results from the test chips demonstrate that the proposed gain cell eDRAMs achieve overall faster system performances and lower static power dissipations than SRAMs in a generic 65 nm low-power (LP) CMOS process. A magnetic tunnel junction (MTJ) scaling scenario and an efficient HSPICE simulation methodology are proposed for exploring the scalability of STT-MRAMs under variation effects from 65 nm to 8 nm. A constant JC0*RA/VDD scaling method is adopted to achieve optimal read and write performances of STT-MRAMs and thermal stabilities for a 10 year retention are achieved by adjusting free layer thicknesses as well as projecting crystalline anisotropy improvements. Studies based on the proposed methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material properties in order to overcome the poor write performance from 22 nm node

Effect of Heat Current on Magnetization Dynamics in Magnetic Insulators and Nanostructures

The term "spin caloritronics" defines a novel branch of spintronics that focuses on the interplay between electron spins with heat currents. In the frame of this research area, this thesis is aimed at investigating the effect of a heat current on magnetization dynamics in two different typologies of systems and materials: magnetic insulators and metallic nanostructures. In the first case we conduct studies on yttrium iron garnet (YIG) samples subjected to a temperature gradient. The irreversible thermodynamics of a continuous medium with magnetic dipoles predicts that a thermal gradient across a YIG slab, in the presence of magnetization waves, produces a magnetic field that is the magnetic analog of the well known Seebeck effect. This thermally induced field can influence the time evolution of the magnetization, in such a way that it is possible to modulate the relaxation of the precession when applying a heat current. We found evidence for such a magnetic Seebeck effect (MSE) by conducting transmission measurements in a thin slab of YIG subjected to an in-plane temperature gradient. We showed how the MSE can modulate the magnetic damping depending on the direction of the propagating magnetostatic modes with respect to the orientation of the temperature gradient. In the second part of the thesis we focus our investigation on metallic nanostructures subjected to a heat current. In a metal, the three-current model (current of entropy, of spin up and spin down electrons) predicts that a heat current induces a spin current which will then influence the magnetization dynamics like a charge-driven spin current would. Hence, we explore what has been called Thermal Spin Torque in electrodeposited Co / Cu / Co asymmetric spin valves placed in the middle of copper nanowires. These samples are fabricated by conventional electrodeposition technique in porous polycarbonate membranes using an original method that allows high frequency electrical measurements. We used a modulated laser to investigate the effect of a temperature gradient. We observed a heat-driven spin torque by measuring electrically the quasi-static magnetic response of a spin valve when subjected to the heat current, generated by two laser diodes heating the electrical contact at one end or the other of the nanowire. Analysing the variation in the resistance induced by a heat-driven spin torque, represented by peaks occurring in correspondence with the GMR transition, we found that a temperature difference of the order of 5 K is sufficient to produce sizeable torque in spin valves

Realization of CoFeB|MgO|CoFeB magnetic tunnel junction devices through materials analysis, process integration and circuit simulation

Spin based magnetic tunnel junctions (MTJs) consist of two ferromagnetic thin films separated by a nonmagnetic insulating barrier. The MTJ exhibits two switchable resistive states, making them ideal candidates for non-volatile memory. The discovery of high Tunneling Magnetoresistance (TMR) in MgO based MTJs has brought spintronics into the forefronts of modern technology. A device structure CoFeB|MgO|CoFeB achieved by physical vapor deposition (PVD) has revolutionized the hard-drive industry to go beyond densities of gigabyte per square inch. There is increasing interest in the application of these devices toward other technical areas, such as sensors, logic and reconfigurable computing. In these structures, the thicknesses of the layers are in the order of a few nanometers. For integration of these devices in other platforms, particularly on silicon, to augment the well-developed CMOS technology, it is imperative to (1) investigate processing constraints, (2) develop appropriate physical models, and (3) build circuit models for effective circuit implementation. The work presented in this dissertation focuses on these three important aspects for the realization of CoFeB|MgO|CoFeB MTJs on silicon. A systematic annealing study has been carried out to investigate the role of boron in the device structure. It has been shown using electron energy loss spectroscopy (EELS), and 2D x-ray diffraction (2D XRD) that boron diffuses into MgO with an activation energy of 1.30.4 eV and facilitates the crystallization of CoFe with (200) out-of-plane oriented crystals, with MgO as a template. The grain size of CoFe has been definitively shown to be smaller than the grain size of MgO, which were otherwise believed to be the same. A process temperature of 385°C has been determined to be the optimum limit of processing. A low temperature (\u3c385°C) process employing standard integrated circuit fabrication techniques has been developed. The partial crystallization of CoFe necessitates the modification of the tunneling model. A new model that combines the Julliëre\u27s, free electron and tight-binding model with the probabilistic distribution of grains on either side of the tunneling barrier has been proposed. This model explains the variation of TMR as a function of temperature in devices made by PVD. A generalized circuit macromodel has been developed representing field-switchable magnetic tunnel junctions (MTJs) characterized by two distinct voltage-dependent resistance values in parallel and antiparallel states. General-purpose subcircuit implementations are designed for a switchable voltage-dependent resistor capable of implementation using any version of SPICE. Transient simulation of a flash-comparator circuit using multiple MTJs in series is successfully demonstrated showing the robustness of the model

Modélisation compacte et conception de circuit à base de jonction tunnel ferroélectrique et de jonction tunnel magnétique exploitant le transfert de spin assisté par effet Hall de spin

Non-volatile memory (NVM) devices have been attracting intensive research interest since they promise to solve the increasing static power issue caused by CMOS technology scaling. This thesis focuses on two fields related to NVM: the one is the ferroelectric tunnel junction (FTJ), which is a recent emerging NVM device. The other is the spin-Hall-assisted spin-transfer torque (STT), which is a recent proposed write approach for the magnetic tunnel junction (MTJ). Our objective is to develop the compact models for these two technologies and to explore their application in the non-volatile circuits through simulation.First, we investigated physical models describing the electrical behaviors of the FTJ such as tunneling resistance, dynamic ferroelectric switching and memristive response. The accuracy of these physical models is validated by a good agreement with experimental results. In order to develop an electrical model available for the circuit simulation, we programmed the aforementioned physical models with Verilog-A language and integrated them together. The developed electrical model can run on Cadence platform (a standard circuit simulation tool) and faithfully reproduce the behaviors of the FTJ.Then, using the developed FTJ model and STMicroelectronics CMOS design kit, we designed and simulated three types of circuits: i) FTJ-based random access memory (FTRAM), ii) two FTJ-based neuromorphic systems, one of which emulates spike-timing dependent plasticity (STDP) learning rule, the other implements supervised learning of logic functions, iii) FTJ-based Boolean logic block, by which NAND and NOR logic are demonstrated. The influences of the FTJ parameters on the performance of these circuits were analyzed based on simulation results.Finally, we focused on the reversal of the perpendicular magnetization driven by spin-Hall-assisted STT in a three-terminal MTJ. In this scheme, two write currents are applied to generate spin-Hall effect (SHE) and STT. Numerical simulation based on Landau-Lifshitz-Gilbert (LLG) equation demonstrates that the incubation delay of the STT can be eliminated by the strong SHE, resulting in ultrafast magnetization switching without the need to strengthen the STT. We applied this novel write approach to the design of the magnetic flip-flop and full-adder. Performance comparison between the spin-Hall-assisted and the conventional STT magnetic circuits were discussed based on simulation results and theoretical models.Les mémoires non-volatiles (MNV) sont l'objet d'un effort de recherche croissant du fait de leur capacité à limiter la consommation statique, qui obère habituellement la réduction des dimensions dans la technologie CMOS. Dans ce contexte, cette thèse aborde plus spécifiquement deux technologies de mémoires non volatiles : d'une part les jonctions tunnel ferroélectriques (JTF), dispositif non volatil émergent, et d'autre part les dispositifs à transfert de spin (TS) assisté par effet Hall de spin (EHS), approche alternative proposée récemment pour écrire les jonctions tunnel magnétiques (JTM). Mon objectif est de développer des modèles compacts pour ces deux technologies et d'explorer, par simulation, leur intégration dans les circuits non-volatiles.J'ai d'abord étudié les modèles physiques qui décrivent les comportements électriques des JTF : la résistance tunnel, la dynamique de la commutation ferroélectrique et leur comportement memristif. La précision de ces modèles physiques est validée par leur bonne adéquation avec les résultats expérimentaux. Afin de proposer un modèle compatible avec les simulateurs électriques standards, nous j'ai développé les modèles physiques mentionnés ci-dessus en langue Verilog-A, puis je les ai intégrés ensemble. Le modèle électrique que j'ai conçu peut être exploité sur la plate-forme Cadence (un outil standard pour la simulation de circuit). Il reproduit fidèlement les comportements de JTF. Ensuite, en utilisant ce modèle de JTF et le design-kit CMOS de STMicroelectronics, j'ai conçu et simulé trois types de circuits: i) une mémoire vive (RAM) basée sur les JTF, ii) deux systèmes neuromorphiques basés sur les JTF, l'un qui émule la règle d'apprentissage de la plasticité synaptique basée sur le décalage temporel des impulsions neuronale (STDP), l'autre mettant en œuvre l'apprentissage supervisé de fonctions logiques, iii) un bloc logique booléen basé sur les JTF, y compris la démonstration des fonctions logiques NAND et NOR. L'influence des paramètres de la JTF sur les performances de ces circuits a été analysée par simulation. Finalement, nous avons modélisé la dynamique de renversement de l'aimantation dans les dispositifs à anisotropie perpendiculaire à transfert de spin assisté par effet Hall de spin dans un JTM à trois terminaux. Dans ce schéma, deux courants d'écriture sont appliqués pour générer l'EHS et le TS. La simulation numérique basée sur l'équation de Landau-Lifshitz-Gilbert (LLG) démontre que le délai d'incubation de TS peut être éliminé par un fort EHS, conduisant à la commutation ultra-rapide de l'aimantation, sans pour autant requérir une augmentation excessive du TS. Nous avons appliqué cette nouvelle méthode d'écriture à la conception d'une bascule magnétique et d'un additionneur 1 bit magnétique. Les performances des circuits magnétiques assistés par l'EHS ont été comparés à ceux écrits par transfert de spin, par simulation et par une analyse fondée sur le modèle théorique