Design and layout strategies for integrated frequency synthesizers with high spectral purity

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequen

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL)

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Elimination of subharmonics in direct look-up table (DLT) sine wave reference generators for low-cost microprocessor-controlled inverters

This paper investigates distortion of an inverter reference waveform generated using a direct look-up (DLT) algorithm. The sources of various distortion components are identified and the implications for application to variable speed drives and grid connected inverters are described. Harmonic and subharmonic distortion mechanisms are analyzed, and compared with experimental results. Analytical methods are derived to determine the occurrence of subharmonics, their number, frequencies and maximum amplitudes. A relationship is established identifying a discrete set of synthesizable frequencies which avoid sub-harmonic distortion as a function of look-up table length and a practical method for calculation of the look-up table indices, based on finite length binary representation, is presented. Real time experimental results are presented to verify the analytical derivations

Digital instrumentation for the measurement of high spectral purity signals

Improvements on electronic technology in recent years have allowed the application of digital techniques in time and frequency metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. The Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs), as the system front-end, set the ultimate performance of the system in terms of noise. The noise characterization of these components will allow performing punctual considerations on the study of the implementation feasibility of new techniques and for the selection of proper components according to the application requirements. Moreover, most commercial platforms based on FPGA are clocked by quartz oscillators whose accuracy and frequency stability are not suitable for many time and frequency applications. In this case, it is possible to take advantage of the internal Phase Locked Loop (PLL) for generating the internal clock from an external frequency reference. However, the PLL phase noise could degrade the oscillator stability thereby limiting the entire system performance becoming a critical component for digital instrumentation. The information available currently in literature, describes in depth the features of these devices at frequency offsets far from the carrier. However, the information close to the carrier is a more important concern for time and frequency applications. In this frame, my PhD work is focused on understanding the limitations of the critical blocks of digital instrumentation for time and frequency metrology. The aim is to characterize the noise introduced by these blocks and in this manner to be able to predict their effects on a specific application. This is done by modeling the noise introduced by each component and by describing them in terms of general and technical parameters. The parameters of the models are identified and extracted through the corresponding method proposed accordingly to the component operation. This work was validated by characterizing a commercially available platform, Red Pitaya. This platform is an open source embedded system whose resolution and speed (14 bit, 125 MSps) are reasonably close to the state of the art of ADCs and DACs (16 bit, 350 MSps or 14 bit, 1 GSps/3GSPs) and it is potentially sufficient for the implementation of a complete instrument. The characterization results lead to the noise limitations of the platform and give a guideline for instrumentation design techniques. Based on the results obtained from the noise characterization, the implementation of a digital instrument for frequency transfer using fiber link was performed on the Red Pitaya platform. In this project, a digital implementation for the detection and compensation of the phase noise induced by the fiber is proposed. The beat note, representing the fiber length variations, is acquired directly with a high speed ADC followed by a fully digital phase detector. Based on the characterization results, it was expected a limitation in the phase noise measurement given by the PLL. First measurements of this implementation were performed using the 150 km-long buried fibers, placed in the same cables between INRiM and the Laboratoire Souterrain de Modane (LSM) on the Italy-France border. The two fibers are joined together at LSM to obtain a 300 km loop with both ends at INRiM. From these results the noise introduced by the digital system was verified in agreement with characterization results. Further test and improvements will be performed for having a finished system which is intended to be used on the Italian Link for Frequency and Time from Turin to Florence that is 642-km long and to its extension in the rest of Italy that is foreseen in the next future. Currently, a higher performance platform is under assessment by applying the tools and concepts developed along the PhD. The purpose of this project is the implementation of a state of the art phasemeter whose architecture is based on the DAC. In order to estimate the ultimate performance of the instrument, the DAC characterization is under development and preliminary measurements are also reported here

Performance Evaluation of wide Bandwidth RF Signal Generator Chip

The work in this paper is to give an overview of the compact wide band RF signal generator board design, emphasizing on the analyses and evaluation of the performance characteristics corresponding to the output signal purity and stability. The paper describes the design aspects involved in developing a reliable RF generating source which includes details regarding the factors that have taken care for optimum output power, spectral purity and noise performance. The simulation results obtained from the tool given by Maxim integrated are used as reference to evaluate the actual board when it is realised. These results are shown here for reference. Design aspects such as the power supply, noise filtering, loop filter component selection board layout consideration along with easy and compact form factor is considered. The board contains not only the signal generator device but also an FPGA from Xilinx to control the device, to make the board more useful for future applications; the board also has an SDRAM and an USB controller. This paper mainly concentrates on to MAX2870 signal generator and simulation results obtained by EE-Sim tool. Since the actual board is still in the process of being developed, the comparison of the actual performance to the simulation performance may not be possible at this point of time but definitely is in pipeline

Telecommunications Division

Spacecraft telecommunication systems - coding methods for phase locked loops, absolute time determination by pulsar, communications elements researc

Development and evaluation of a programmable radio frequency signal

ThesisMost commercially available signal generators make use of a phase-locked loop in combination with analogue frequency synthesis to generate the desired frequency range. Advances in the development of components being used in digital frequency synthesis have made the use of direct digital synthesis (DDS) a viable option in radio frequency (RF) signal generation. The project consists of designing the interfacing between a DDS unit and a microcontroller to provide a versatile frequency generator in the lower high frequency (HF) spectrum. The research was aimed at testing the following hypothesis: A programmable Radio Frequency signal generator can be developed, using a DDS-based system with a microcontroller providing the required intelligence. A continuously variable frequency range in 1 Hz steps over a spectrum of 0- 10 MHz can be achieved. The following features were included in the design of the signal generator: • Setting the generator to a specific frequency; • Displaying the frequency and prompts from the microcontroller on a liquid crystal display; • Interfacing with a keypad; • Interfacing with a personal computer for remote RS232 operation; • Interfacing with a rotary optical encoder for up-and-down frequency control; • Sweeping of a range of frequencies; • Setting the step size of frequency increments; • Frequency shift keying (FSK) capability. The above features allowed ample demonstration of the software control over the associated hardware and enabled easy evaluation of the product. To evaluate the product, it was decided to concentrate on the following measurable aspects of a typical radio frequency (RF) signal generator: • The accuracy of the output frequency; • Evaluating the frequency range limits of the generator; • Making a spectral analysis of the output signal. During the execution of the project, insight was gained with respect to the following: • DDS theory; • DDS hardware interfacing; • C-programming as well as using the versatile DSSOOO microcontroller; • The importance of sound design principles in a hybrid digital and analogue radio frequency project. • Setting the step size of frequency increments; • Frequency shift keying (FSK) capability. The above features allowed ample demonstration of the software control over the associated hardware and enabled easy evaluation of the product. To evaluate the product, it was decided to concentrate on the following measurable aspects of a typical radio frequency (RF) signal generator: • The accuracy of the output frequency; • Evaluating the frequency range limits of the generator; • Making a spectral analysis of the output signal. During the execution of the project, insight was gained with respect to the following: • DDS theory; • DDS hardware interfacing; • C-programming as well as using the versatile DSSOOO microcontroller; • The importance of sound design principles in a hybrid digital and analogue radio frequency project