Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Limitations of PLL simulation: hidden oscillations in MatLab and SPICE

Nonlinear analysis of the phase-locked loop (PLL) based circuits is a challenging task, thus in modern engineering literature simplified mathematical models and simulation are widely used for their study. In this work the limitations of numerical approach is discussed and it is shown that, e.g. hidden oscillations may not be found by simulation. Corresponding examples in SPICE and MatLab, which may lead to wrong conclusions concerning the operability of PLL-based circuits, are presented

Theory of phaselock techniques as applied to aerospace transponders

Phaselock techniques as applied to aerospace transponder

Phase-locked Loop Dynamics in the Presence of Noise by Fokker-planck Techniques

Phase error behavior of phase-locked loop tracking system in presence of gaussian noise determined by fokker-planck equatio

Special studies of AROD systems, concepts and designs Final report

Design and evaluation of development model for airborne range and orbit determination syste

Diagnosis of Inter-Turn Short Circuit for a Polyphase Induction Motor in Closed-Loop Vector-Controlled Drives

The main objective of this paper is to develop and experimentally verify a new technique to detect an inter-turn short circuit in one phase of a stator winding of an induction motor energized from a vector-controlled drive. This is in order to overcome the fault masking difficulties associated with the concept of depending on the actual magnetic field pendulous oscillation between the conventional voltage and current space vectors with respect to a reference that is unaltered by the compensation action of the drive. This technique is based on the flux pendulous oscillation phenomenon. This flux pendulous oscillation is also described in this paper, this in addition to the magnetic field pendulous oscillation previously addressed in prior publications. The new approach has been verified through experimental results which are represented here