A Motion Estimation based Algorithm for Encoding Time Reduction in HEVC

High Efficiency Video Coding (HEVC) is a video compression standard that offers 50% more efficiency at the expense of high encoding time contrasted with the H.264 Advanced Video Coding (AVC) standard. The encoding time must be reduced to satisfy the needs of real-time applications. This paper has proposed the Multi- Level Resolution Vertical Subsampling (MLRVS) algorithm to reduce the encoding time. The vertical subsampling minimizes the number of Sum of Absolute Difference (SAD) computations during the motion estimation process. The complexity reduction algorithm is also used for fast coding the coefficients of the quantised block using a flag decision. Two distinct search patterns are suggested: New Cross Diamond Diamond (NCDD) and New Cross Diamond Hexagonal (NCDH) search patterns, which reduce the time needed to locate the motion vectors. In this paper, the MLRVS algorithm with NCDD and MLRVS algorithm with NCDH search patterns are simulated separately and analyzed. The results show that the encoding time of the encoder is decreased by 55% with MLRVS algorithm using NCDD search pattern and 56% with MLRVS using NCDH search pattern compared to HM16.5 with Test Zone (TZ) search algorithm. These results are achieved with a slight increase in bit rate and negligible deterioration in output video quality

Layer-Aware Forward Error Correction for Mobile Broadcast of Layered Media

The bitstream structure of layered media formats such as scalable video coding (SVC) or multiview video coding (MVC) opens up new opportunities for their distribution in Mobile TV services. Features like graceful degradation or the support of the 3-D experience in a backwards-compatible way are enabled. The reason is that parts of the media stream are more important than others with each part itself providing a useful media representation. Typically, the decoding of some parts of the bitstream is only possible, if the corresponding more important parts are correctly received. Hence, unequal error protection (UEP) can be applied protecting important parts of the bitstream more strongly than others. Mobile broadcast systems typically apply forward error correction (FEC) on upper layers to cope with transmission errors, which the physical layer FEC cannot correct. Today's FEC solutions are optimized to transmit single layer video. The exploitation of the dependencies in layered media codecs for UEP using FEC is the subject of this paper. The presented scheme, which is called layer-aware FEC (LA-FEC), incorporates the dependencies of the layered video codec into the FEC code construction. A combinatorial analysis is derived to show the potential theoretical gain in terms of FEC decoding probability and video quality. Furthermore, the implementation of LA-FEC as an extension of the Raptor FEC and the related signaling are described. The performance of layer-aware Raptor code with SVC is shown by experimental results in a DVB-H environment showing significant improvements achieved by LA-FEC. © 2011 IEEE.Hellge, C.; Gómez Barquero, D.; Schierl, T.; Wiegand, T. (2011). Layer-Aware Forward Error Correction for Mobile Broadcast of Layered Media. IEEE Transactions on Multimedia. 13(3):551-562. doi:10.1109/TMM.2011.2129499S55156213

Visual Saliency Estimation Via HEVC Bitstream Analysis

Abstract Since Information Technology developed dramatically from the last century 50's, digital images and video are ubiquitous. In the last decade, image and video processing have become more and more popular in biomedical, industrial, art and other fields. People made progress in the visual information such as images or video display, storage and transmission. The attendant problem is that video processing tasks in time domain become particularly arduous. Based on the study of the existing compressed domain video saliency detection model, a new saliency estimation model for video based on High Efficiency Video Coding (HEVC) is presented. First, the relative features are extracted from HEVC encoded bitstream. The naive Bayesian model is used to train and test features based on original YUV videos and ground truth. The intra frame saliency map can be achieved after training and testing intra features. And inter frame saliency can be achieved by intra saliency with moving motion vectors. The ROC of our proposed intra mode is 0.9561. Other classification methods such as support vector machine (SVM), k nearest neighbors (KNN) and the decision tree are presented to compare the experimental outcomes. The variety of compression ratio has been analysis to affect the saliency

Algorithms and methods for video transcoding.

Video transcoding is the process of dynamic video adaptation. Dynamic video adaptation can be defined as the process of converting video from one format to another, changing the bit rate, frame rate or resolution of the encoded video, which is mainly necessitated by the end user requirements. H.264 has been the predominantly used video compression standard for the last 15 years. HEVC (High Efficiency Video Coding) is the latest video compression standard finalised in 2013, which is an improvement over H.264 video compression standard. HEVC performs significantly better than H.264 in terms of the Rate-Distortion performance. As H.264 has been widely used in the last decade, a large amount of video content exists in H.264 format. There is a need to convert H.264 video content to HEVC format to achieve better Rate-Distortion performance and to support legacy video formats on newer devices. However, the computational complexity of HEVC encoder is 2-10 times higher than that of H.264 encoder. This makes it necessary to develop low complexity video transcoding algorithms to transcode from H.264 to HEVC format. This research work proposes low complexity algorithms for H.264 to HEVC video transcoding. The proposed algorithms reduce the computational complexity of H.264 to HEVC video transcoding significantly, with negligible loss in Rate-Distortion performance. This work proposes three different video transcoding algorithms. The MV-based mode merge algorithm uses the block mode and MV variances to estimate the split/non-split decision as part of the HEVC block prediction process. The conditional probability-based mode mapping algorithm models HEVC blocks of sizes 16×16 and lower as a function of H.264 block modes, H.264 and HEVC Quantisation Parameters (QP). The motion-compensated MB residual-based mode mapping algorithm makes the split/non-split decision based on content-adaptive classification models. With a combination of the proposed set of algorithms, the computational complexity of the HEVC encoder is reduced by around 60%, with negligible loss in Rate-Distortion performance, outperforming existing state-of-art algorithms by 20-25% in terms of computational complexity. The proposed algorithms can be used in computation-constrained video transcoding applications, to support video format conversion in smart devices, migration of large-scale H.264 video content from host servers to HEVC, cloud computing-based transcoding applications, and also to support high quality videos over bandwidth-constrained networks

Définition et implantation matérielle d'un estimateur de mouvement configurable pour la compression vidéo adaptative

L objectif de cette thèse est la conception d une plateforme de compression vidéo de nouvelle génération à haut degré d adaptation vis-à-vis de l environnement. Ce besoin d adaptabilité a plusieurs origines. D une part les systèmes actuels visent à s adapter à la diversité et l hétérogénéité des médias et des terminaux actuels. D autre part, l exploitation de l information contenue dans une scène vidéo dépend de l application visée et des besoins des utilisateurs. Ainsi, l information peut être exploitée de manière complètement inhomogène spatialement ou temporellement. En effet, l exploitation spatiale de la scène peut être irrégulière par définition, par la définition automatique ou manuelle de zones d intérêts dans l image. La qualité de la vidéo, donc de la compression, doit pouvoir s adapter afin de limiter la quantité de donnée à transmettre. Cette qualité est donc dépendante de l évolution de la scène vidéo elle-même. Une architecture matérielle configurable a été proposée dans cette thèse permettant de supporter différents algorithmes de recherche en offrant une précision subpixélique.La synthèse des travaux menés dans ce domaine et la comparaison objective des résultats obtenus par rapport à l'état de l'art. L architecture proposée est synthétisée à base d un FPGA Virtex 6 FPGA, les résultats obtenus pourraient traiter l'estimation du mouvement pixélique avec un flux vidéo haute définition (HD 1080), respectivement à 13 images par seconde en utilisant la stratégie de recherche exhaustive (108K Macroblocs/s) et jusqu'à 223 images par seconde avec la recherche selon un grille en diamant (1,8 M Macroblocs /s). En outre le raffinement subpixélique en quart-pel est réalisé à Macroblocs 232k/ sThe aim of this thesis was to define and implement a hardware architecture of a configurable motion estimation capable of supporting various search strategies with the desired accuracy for adaptive video compression. This need for adaptability had several origins. Firstly, the current systems are designed to adapt to the diversity and heterogeneity of current terminals and media. Secondly, the use of information contained in a video scene depends on the intended applications and user needs. This objective scoring modestly in the challenge offered by the development of digital video requires a faster processing and a high compression ratio.In this thesis, a flexible hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search as well as variable block size to be selected and adjusted. Hence, this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quarter-pelrefinement, as described in H.264. The proposed low-cost architecture based on Virtex 6 FPGA canprocess integer motion estimation on 1080 HD video streams, respectively, at 13 fps using full search strategy (108k Macroblocks/s) and up to 223 fps using diamond search (1.8M Macroblocks/s). Moreover subpel refinement in quarter-pel mode is performed at 232k Macroblocks/sDIJON-BU Doc.électronique (212319901) / SudocSudocFranceF