Application of fuzzy logic-neural network based reinforcement learning to proximity and docking operations: Special approach/docking testcase results

As part of the RICIS project, the reinforcement learning techniques developed at Ames Research Center are being applied to proximity and docking operations using the Shuttle and Solar Maximum Mission (SMM) satellite simulation. In utilizing these fuzzy learning techniques, we use the Approximate Reasoning based Intelligent Control (ARIC) architecture, and so we use these two terms interchangeably to imply the same. This activity is carried out in the Software Technology Laboratory utilizing the Orbital Operations Simulator (OOS) and programming/testing support from other contractor personnel. This report is the final deliverable D4 in our milestones and project activity. It provides the test results for the special testcase of approach/docking scenario for the shuttle and SMM satellite. Based on our experience and analysis with the attitude and translational controllers, we have modified the basic configuration of the reinforcement learning algorithm in ARIC. The shuttle translational controller and its implementation in ARIC is described in our deliverable D3. In order to simulate the final approach and docking operations, we have set-up this special testcase as described in section 2. The ARIC performance results for these operations are discussed in section 3 and conclusions are provided in section 4 along with the summary for the project

Search Based Software Engineering

The articles in this special section focus on search-based software engineering. Search Based Software Engineering (SBSE) consists of the application of computational intelligence (CI) algorithms to hard optimization problems in software engineering (SE). It has become an important application field for CI. The term SBSE was coined by Harman and Jones in 2001, although there was work on the application of CI algorithms to SE before this date. After more than fifteen years development, CI algorithms have been used to solve SE tasks in almost all the stages of an SE lifecycle, including requirements, designing, coding, testing and maintenance. solved by three steps

Special Section on Emerging and Impacting Trends on Computer Arithmetic

The papers in this special section focus on emerging and impacting trends on computer arithmetic. The computer arithmetic. field encompasses the definition and standardization of arithmetic systems for computers. It also deals with issues pertaining to hardware and software implementations, testing, and verification. Researchers and practitioners of this field also work on challenges associated with using Computer Arithmetic to perform scientific and engineering calculations. As such, Computer Arithmetic can be regarded as a truly multi-disciplinary field, which builds upon mathematics, computer science and electrical engineering. Thus, the range of topics addressed by Computer Arithmetic is generally very broad, spanning from highly theoretical to extremely practical contributions. Computer Arithmetic has been an active research field since the advent of computers, and it is progressively evolving following continuously advancements in technology

Research of the metal fatique crack development kinetics basing on digital 3d model

Отримано цифрову 3D-модель тріщини (ЦМТ) металу у вигляді поверхні в просторі. При розробленні ЦМТ використано стереопари знімків, які отримано за допомогою растрового електронного мікроскопа. За результатами обробки двох знімків стереопари визначено координати одиничних точок у просторі на поверхні тріщини. ЦМТ утворена шляхом інтерполяції точкових даних із використанням програмного забезпечення Surfer 10. Здійснено аналіз тріщини з використання ЦМТ і визначено геометричні розміри фронту тріщини у її поперечному перерізі.The paper presents a new approach to obtain data on geometrical parameters of fatigue cracks, which are crucial in kinetics research of their development. The subject of research was fatigue cracks of the metallic samples. Cracks were formed by testing of samples with the artificial defects on the investigation equipment applying different number of loading cycles. Technology of obtaining digital 3D model crack (DMC) of metal crack is described. Treating the fatigue crack as a fracture surface in metal, photogrammetry methods were applied to create digital 3D model of the crack. Stereo pair images, which had been obtained by means of REM 6I raster electron microscope, were used while developing DMC. According to the results of processing two stereo pair images coordinates of single points in space on the crack surface were determined. DMC was formed by interpolation of point data taking advantage of software Surfer 10. DMC was presented as the graphic three-dimensional image of crack surface in a vector form. Obtained DMC can be considered under various angles, analyzed with special calculation software modules. Analysis of the crack was made with application of DMC. Geometric dimensions of the crack front in its cross-section were determined. Obtained cross-section of the crack allows to approximate its front line and to choose reasonably the typical shape of the crack. Besides, in the case of complex configuration of crack shape the obtained data on its cross section can be used to calculate stress intensity factor (SIF). It is shown, that in the crack cross section the front of its propagation is a line of complex configuration forming sharp rim of the tunnel shape. Penetration of the crack inside the metal increases the value of stress intensity factor (SIF) by 20 – 40% especially on the final stages of the crack growth. The obtained results are recommended to be used while determining stress intensity factor of cracks with complex configuration

Design of a Channel Error Simulator using Virtual Instrument Techniques for the Initial Testing of TCP/IP and SCPS Protocols

There exists a need for designers and developers to have a method to conveniently test a variety of communications parameters for an overall system design. This is no different when testing network protocols as when testing modulation formats. In this report, we discuss a means of providing a networking test device specifically designed to be used for space communications. This test device is a PC-based Virtual Instrument (VI) programmed using the LabVIEW(TM) version 5 software suite developed by National Instruments(TM)TM. This instrument was designed to be portable and usable by others without special, additional equipment. The programming was designed to replicate a VME-based hardware module developed earlier at New Mexico State University (NMSU) and to provide expanded capabilities exceeding the baseline configuration existing in that module. This report describes the design goals for the VI module in the next section and follows that with a description of the design of the VI instrument. This is followed with a description of the validation tests run on the VI. An application of the error-generating VI to networking protocols is then given

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints