Universal Three Dimensional Optical Logic

Modern integrated circuits are essentially two-dimensional (2D). Partial three-dimensional (3D) integration and 3D-transistor-level integrated circuits have long been anticipated as routes to improve the performance, cost and size of electronic computing systems. Even as electronics approach fundamental limits however, stubborn challenges in 3D circuits, and innovations in planar technology have delayed the dimensional transition. Optical computing offers potential for new computing approaches, substantially greater performance and would complement technologies in optical interconnects and data storage. Nevertheless, despite some progress, few proposed optical transistors possess essential features required for integration into real computing systems. Here we demonstrate a logic gate based on universal features of nonlinear wave propagation: spatiotemporal instability and collapse. It meets the scaling criteria and enables a 3D, reconfigurable, globally-hyperconnected architecture that may achieve an exponential speed up over conventional platforms. It provides an attractive building block for future optical computers, where its universality should facilitate flexible implementations.Comment: manuscript (5 pages, 3 figures) with supplementary information (6 pages, 5 figures

Introduction to Graphene Electronics -- A New Era of Digital Transistors and Devices

The speed of silicon-based transistors has reached an impasse in the recent decade, primarily due to scaling techniques and the short-channel effect. Conversely, graphene (a revolutionary new material possessing an atomic thickness) has been shown to exhibit a promising value for electrical conductivity. Graphene would thus appear to alleviate some of the drawbacks associated with silicon-based transistors. It is for this reason why such a material is considered one of the most prominent candidates to replace silicon within nano-scale transistors. The major crux here, is that graphene is intrinsically gapless, and yet, transistors require a band-gap pertaining to a well-defined ON/OFF logical state. Therefore, exactly as to how one would create this band-gap in graphene allotropes is an intensive area of growing research. Existing methods include nano-ribbons, bilayer and multi-layer structures, carbon nanotubes, as well as the usage of the graphene substrates. Graphene transistors can generally be classified according to two working principles. The first is that a single graphene layer, nanoribbon or carbon nanotube can act as a transistor channel, with current being transported along the horizontal axis. The second mechanism is regarded as tunneling, whether this be band-to-band on a single graphene layer, or vertically between adjacent graphene layers. The high-frequency graphene amplifier is another talking point in recent research, since it does not require a clear ON/OFF state, as with logical electronics. This paper reviews both the physical properties and manufacturing methodologies of graphene, as well as graphene-based electronic devices, transistors, and high-frequency amplifiers from past to present studies. Finally, we provide possible perspectives with regards to future developments.Comment: This is an updated version of our review article, due to be published in Contemporary Physics (Sept 2013). Included are updated references, along with a few minor corrections. (45 pages, 19 figures

Electron Spin for Classical Information Processing: A Brief Survey of Spin-Based Logic Devices, Gates and Circuits

In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information-processing device invariably causes current flow and an associated dissipation. Replacing charge with the "spin" of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient "green electronics". This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation.Comment: Topical Revie

Application of Graphene within Optoelectronic Devices and Transistors

Scientists are always yearning for new and exciting ways to unlock graphene's true potential. However, recent reports suggest this two-dimensional material may harbor some unique properties, making it a viable candidate for use in optoelectronic and semiconducting devices. Whereas on one hand, graphene is highly transparent due to its atomic thickness, the material does exhibit a strong interaction with photons. This has clear advantages over existing materials used in photonic devices such as Indium-based compounds. Moreover, the material can be used to 'trap' light and alter the incident wavelength, forming the basis of the plasmonic devices. We also highlight upon graphene's nonlinear optical response to an applied electric field, and the phenomenon of saturable absorption. Within the context of logical devices, graphene has no discernible band-gap. Therefore, generating one will be of utmost importance. Amongst many others, some existing methods to open this band-gap include chemical doping, deformation of the honeycomb structure, or the use of carbon nanotubes (CNTs). We shall also discuss various designs of transistors, including those which incorporate CNTs, and others which exploit the idea of quantum tunneling. A key advantage of the CNT transistor is that ballistic transport occurs throughout the CNT channel, with short channel effects being minimized. We shall also discuss recent developments of the graphene tunneling transistor, with emphasis being placed upon its operational mechanism. Finally, we provide perspective for incorporating graphene within high frequency devices, which do not require a pre-defined band-gap.Comment: Due to be published in "Current Topics in Applied Spectroscopy and the Science of Nanomaterials" - Springer (Fall 2014). (17 pages, 19 figures

Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970

Mass memory system for advanced spacecraf

The design and performance of a high efficiency power conversion system for use with the WJ-274 traveling-wave tube Final report, phase I

Design and performance of high efficiency power conversion system for use with WJ-274 traveling wave tube compatible with extraterrestrial environments - spaceborne communication

PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.Universidad Autónoma de Tlaxcala CACyPI-UATx-2017Program to Strengthen Quality in Educational Institutions C/PFCE-2016-29MSU0013Y-07-23National Council for Science and Technology 237991 22284

Optimization study of high power static inverters and converters Final report

Optimization study and basic performance characteristics for conceptual designs for high power static inverter