588 research outputs found
Fixed-Parameter Algorithms for Rectilinear Steiner tree and Rectilinear Traveling Salesman Problem in the plane
Given a set of points with their pairwise distances, the traveling
salesman problem (TSP) asks for a shortest tour that visits each point exactly
once. A TSP instance is rectilinear when the points lie in the plane and the
distance considered between two points is the distance. In this paper, a
fixed-parameter algorithm for the Rectilinear TSP is presented and relies on
techniques for solving TSP on bounded-treewidth graphs. It proves that the
problem can be solved in where denotes the
number of horizontal lines containing the points of . The same technique can
be directly applied to the problem of finding a shortest rectilinear Steiner
tree that interconnects the points of providing a
time complexity. Both bounds improve over the best time bounds known for these
problems.Comment: 24 pages, 13 figures, 6 table
Routing for analog chip designs at NXP Semiconductors
During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP.
This resulted in an heuristic approach, which we presented at the end of the
week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach
Speeding-up Dynamic Programming with Representative Sets - An Experimental Evaluation of Algorithms for Steiner Tree on Tree Decompositions
Dynamic programming on tree decompositions is a frequently used approach to
solve otherwise intractable problems on instances of small treewidth. In recent
work by Bodlaender et al., it was shown that for many connectivity problems,
there exist algorithms that use time, linear in the number of vertices, and
single exponential in the width of the tree decomposition that is used. The
central idea is that it suffices to compute representative sets, and these can
be computed efficiently with help of Gaussian elimination.
In this paper, we give an experimental evaluation of this technique for the
Steiner Tree problem. A comparison of the classic dynamic programming algorithm
and the improved dynamic programming algorithm that employs the table reduction
shows that the new approach gives significant improvements on the running time
of the algorithm and the size of the tables computed by the dynamic programming
algorithm, and thus that the rank based approach from Bodlaender et al. does
not only give significant theoretical improvements but also is a viable
approach in a practical setting, and showcases the potential of exploiting the
idea of representative sets for speeding up dynamic programming algorithms
Minimizing the stabbing number of matchings, trees, and triangulations
The (axis-parallel) stabbing number of a given set of line segments is the
maximum number of segments that can be intersected by any one (axis-parallel)
line. This paper deals with finding perfect matchings, spanning trees, or
triangulations of minimum stabbing number for a given set of points. The
complexity of these problems has been a long-standing open question; in fact,
it is one of the original 30 outstanding open problems in computational
geometry on the list by Demaine, Mitchell, and O'Rourke. The answer we provide
is negative for a number of minimum stabbing problems by showing them NP-hard
by means of a general proof technique. It implies non-trivial lower bounds on
the approximability. On the positive side we propose a cut-based integer
programming formulation for minimizing the stabbing number of matchings and
spanning trees. We obtain lower bounds (in polynomial time) from the
corresponding linear programming relaxations, and show that an optimal
fractional solution always contains an edge of at least constant weight. This
result constitutes a crucial step towards a constant-factor approximation via
an iterated rounding scheme. In computational experiments we demonstrate that
our approach allows for actually solving problems with up to several hundred
points optimally or near-optimally.Comment: 25 pages, 12 figures, Latex. To appear in "Discrete and Computational
Geometry". Previous version (extended abstract) appears in SODA 2004, pp.
430-43
Shortest Paths and Steiner Trees in VLSI Routing
Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer
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