Open source microprocessor and on-chip-bus for system-on-chip

A System-On-Chip (SoC) is a complex integrated circuit that combines blocks of processor, memory and peripheral devices in one chip. SoCs often form the main or the only component of embedded systems. The advantages of the SoC include improvements in performance, size, reliability, power dissipation, cost, and design turn-around time. The hardware blocks – sometimes referred to as intellectual property cores or just IPs – are connected using a proprietary or open on-chip bus (OCB). The SoCs may be fabricated as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). The non-recurring engineering (NRE) costs for ASICs are much higher although the unit cost for the finished product is lower. For simpler designs and/or lower production runs, FPGAs are usually more cost-effective. One of the costs in implementing an SoC is acquiring the source code or designing the required cores. An approach for reducing costs is to use open source hardware. Open source cores have the advantages of zero license and royalty cost, ability to modify the cores at will, no limitation on supply and maintenance, portability and simplified prototyping. We discuss our implementation of a skeleton SoC incorporating a DLX processor, the Wishbone on-chip bus, and a memory system. The processor bus- memory combination forms a foundation to which a designer can add more cores such as memory and peripherals as long as they comply with the Wishbone protocol. The DLX processor and memory are described in VHDL, while the Wishbone module is in Verilog HDL. Quartus II software is used to synthesize, compile and verify the functionality of CPU and Wishbone by simulation and timing analysis. The partial SoC system is implemented in Altera APEX20KE200 FPGA board. Nios, which is the core processor in the FPGA board, is used as an intermediate processor which communicates with DLX and the rest of the system via Avalon Bus Protocol to verify system operation and functionality in real hardware environment

A system-level multiprocessor system-on-chip modeling framework

We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework

Unified System on Chip RESTAPI Service (USOCRS)

Abstract. This thesis investigates the development of a Unified System on Chip RESTAPI Service (USOCRS) to enhance the efficiency and effectiveness of SOC verification reporting. The research aims to overcome the challenges associated with the transfer, utilization, and interpretation of SoC verification reports by creating a unified platform that integrates various tools and technologies. The research methodology used in this study follows a design science approach. A thorough literature review was conducted to explore existing approaches and technologies related to SOC verification reporting, automation, data visualization, and API development. The review revealed gaps in the current state of the field, providing a basis for further investigation. Using the insights gained from the literature review, a system design and implementation plan were developed. This plan makes use of cutting-edge technologies such as FASTAPI, SQL and NoSQL databases, Azure Active Directory for authentication, and Cloud services. The Verification Toolbox was employed to validate SoC reports based on the organization’s standards. The system went through manual testing, and user satisfaction was evaluated to ensure its functionality and usability. The results of this study demonstrate the successful design and implementation of the USOCRS, offering SOC engineers a unified and secure platform for uploading, validating, storing, and retrieving verification reports. The USOCRS facilitates seamless communication between users and the API, granting easy access to vital information including successes, failures, and test coverage derived from submitted SoC verification reports. By automating and standardizing the SOC verification reporting process, the USOCRS eliminates manual and repetitive tasks usually done by developers, thereby enhancing productivity, and establishing a robust and reliable framework for report storage and retrieval. Through the integration of diverse tools and technologies, the USOCRS presents a comprehensive solution that adheres to the required specifications of the SOC schema used within the organization. Furthermore, the USOCRS significantly improves the efficiency and effectiveness of SOC verification reporting. It facilitates the submission process, reduces latency through optimized data storage, and enables meaningful extraction and analysis of report data

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications