A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Multi-harmonic Modeling of Low-power PWM DC-DC Converter

Modeling and simulation of switched-mode Pulse Width Modulated (PWM) DC-DC converters form an essential ingredient in the analysis and design process of integrated circuits. In this research work, we present a novel large-signal modeling technique for low-power PWM DC-DC converters. The proposed model captures not only the time-averaged response within each moving switching cycle but also high-order harmonics of an arbitrary degree, hence modeling both the average component and ripple very accurately. The proposed model retains the inductor current as a state variable and accurately captures the circuit dynamics even in the transient state. By continuously monitoring state variables, our model seamlessly transitions between the continuous conduction mode (CCM) and discontinuous conduction mode (DCM), which often occurs in low-power applications. The nonlinearities of devices are also considered and efficiently evaluated resulting in a significant improvement in model accuracy. With a system decoupling technique, the DC response of the model is decoupled from higher-order harmonics, providing additional simulation speedups. For a number of converter designs, the proposed model obtains up to 10x runtime speedups over transistor-level transient simulation with a maximum output voltage error less than 4%

Computer Aided Analysis of Periodically Switched Linear Networks

Interest in analysing periodically switched linear networks has developed in response to the rapid development of sampled data communications systems. In particular, integrated circuit switched capacitor networks play an important part in modern analogue signal processing systems. This thesis addresses the problem of developing techniques for analysing periodically switched linear networks in the time and frequency domains that are suited to computer implementation and therefore facilitate the development of efficient computer aided analysis tools for these networks. Systems of large sparse complex linear equations arise in many network analysis problems and efficient techniques for solving these systems are crucial to the analysis methods developed in this thesis. By extending the concept of sparsity to include the type of the nonzero elements, very efficient solution and optimal ordering algorithms are developed. A new method for computing the time domain response of linear networks is presented. The method is based on numerical inversion of the Laplace transform and polynomial approximation of the excitations. This high accuracy method is well suited to solving large stiff systems and is extremely efficient. The method is extended to periodically switched linear networks and provides the basis for frequency domain analysis. A new frequency domain analysis method is presented that is orders of magnitude faster than existing techniques. This efficiency is achieved by developing a formulation such that AC analysis is not required, which allows the system to be solved as a discrete system. A special system compression reduces the solution of this discrete system to the solution of the network in one phase only. This solution step, which ordinarily requires O(N3) operations, is made more efficient by reducing the system to upper Hessenberg form in a preprocessing step, which then reduces the solution cost to O(N2) operations

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281